Programmable Logic Power Domains With Selectable Voltage Regulation

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Solution Overview

Problem

Conventional programmable semiconductor devices like FPGAs and PLDs are less power efficient, limiting their flexibility and ability to meet the demands of low-power consumption required by modern digital communication, AI, and IoT applications.

Innovation Solution

A semiconductor device with a selectable power regulator that allows multiple power domains within a single die, enabling different regions to operate at varying voltages, facilitating power management and efficiency through a configurable power regulator that provides specific voltage outputs to different regions based on enabling inputs.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If a conventional PSD uses a single power domain for the entire chip, then the device complexity is low and ease of manufacture is high, but power consumption is high and power efficiency is poor

Engineering Contradiction:
Improvepower consumptionVSAvoidpower domain structure
Core Design Contradiction:
Use of energy by moving objectVSDevice complexity

Solution Approach 1:

The patent divides the semiconductor chip into multiple power domains, where each domain can be independently powered and controlled. This segmentation allows different regions of the chip to operate at different voltage levels, enabling selective power management and reducing overall power consumption while maintaining the ability to program logic functions across multiple voltage domains

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements dynamic power management by allowing the programmable logic device to selectively enable or disable power domains based on operational requirements. The device can dynamically adjust which voltage domains are active, optimizing power consumption during different operational states while maintaining flexibility in logic function configuration

Inventive Principle:
Principle #15Dynamics

2Loss of energy

If a PSD is designed with multiple power domains, then power efficiency improves and power consumption decreases, but device complexity increases

Engineering Contradiction:
Improvepower efficiencyVSAvoidpower regulator structure
Core Design Contradiction:
Loss of energyVSDevice complexity

Solution Approach 1:

The patent employs a universal power regulator architecture that can serve multiple power domains from a single regulatory structure. This multi-functional regulator is capable of providing different voltage levels to different domains simultaneously, reducing the need for separate regulators for each domain and thereby limiting the increase in device complexity while maintaining power efficiency benefits

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Adaptability or versatility

If conventional PSDs operate at fixed voltage levels, then manufacturing precision requirements are lower and ease of manufacture is higher, but adaptability to different power requirements is limited

Engineering Contradiction:
Improvevoltage domain configurationVSAvoidvoltage domain implementation
Core Design Contradiction:
Adaptability or versatilityVSManufacturing precision

Solution Approach 1:

The patent implements local quality by allowing different regions of the semiconductor chip to have different voltage characteristics and power domain configurations. Each power domain can be independently optimized for its specific functional requirements, enabling local adaptation to different power needs while using standardized manufacturing processes for the overall device structure

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS11496135B2Method and apparatus for providing multiple power domains a programmable semiconductor device
Publication Date: 2022.11.08 GOWIN SEMICON CORP LTD
  • US11496135B2 patent drawing
  • US11496135B2 patent drawing
  • US11496135B2 patent drawing

AI summary

A semiconductor device, able to be selectively configured to perform one or more user defined logic functions, includes a semiconductor die and a selectable power regulator. The semiconductor die, in one aspect, includes a first region and a second region. The first region is operatable to perform a first set of logic functions based on a first power domain having a first voltage. The second region is configured to perform a second set of logic functions based on a second power domain having a second voltage. The selectable power regulator, in one embodiment, provides the second voltage for facilitating the second power domain in the second region of the semiconductor die in response to at least one enabling input from the first region of the semiconductor die.