Logic Cell-Based PUF Generator Circuit Design
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Solution Overview
Problem
SRAM-based PUF generators are inefficient due to layout design rules requiring extra distance to isolate SRAM arrays from other logic transistors, necessitating a more compact and efficient design.
Innovation Solution
A PUF generator based on logic transistors using a PUF cell array with bit cells configured in a column-row layout, employing 12-T or 7-T SRAM bit cells with cross-coupled inverters that eliminate the need for a sense amplifier, allowing for self-sensing and reducing the complexity and cost of the design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If SRAM-based PUF generator uses conventional layout design rules to isolate SRAM arrays from other logic transistors, then isolation and reliability are improved, but area efficiency and compactness deteriorate
Solution Approach 1:
The patent merges the PUF cell structure with logic circuit transistor rules, eliminating the need for separate SRAM array isolation. The PUF cells are directly integrated with logic transistors using the same layout design rules, removing the requirement for extra isolation distance while maintaining reliability through the inherent logic circuit structure.
Solution Approach 2:
The patent changes the fundamental design parameters from SRAM layout rules to logic circuit transistor rules. This parameter change allows PUF cells to be constructed using standard logic transistors with conventional layout spacing, eliminating the need for extended isolation distances while maintaining functional reliability through the logic circuit operation modes.
2Reliability
If SRAM-based PUF generator follows conventional isolation design rules, then manufacturing reliability is improved, but manufacturing efficiency and compactness worsen
Solution Approach 1:
The patent combines PUF cell functionality with logic circuit implementation, allowing both to be manufactured using the same standard logic transistor processes and layout rules. This merging eliminates the need for separate SRAM manufacturing steps and isolation structures, improving manufacturing efficiency while maintaining reliability through standardized processes.
3Device complexity
If PUF cell uses cross-coupled inverters without sense amplifier, then device complexity is reduced, but measurement precision may deteriorate
Solution Approach 1:
The patent implements self-sensing capability directly within the cross-coupled inverter structure of each PUF cell. The inverters inherently provide the feedback mechanism needed for stable output detection without requiring external sense amplifiers. The circuit uses its own internal signal paths and feedback loops to maintain measurement precision, eliminating the need for additional sensing components.
Data Source
AI summary
Disclosed is a physical unclonable function generator circuit and testing method. In one embodiment, a physical unclonable function (PUF) generator includes: a PUF cell array comprising a plurality of bit cells configured in a plurality of columns and at least one row, wherein each of the plurality of columns is coupled to at least two pre-discharge transistors, and each of the plurality of bit cells comprises at least one enable transistor, at least two access transistors, and at least two storage nodes, and a PUF control circuit coupled to the PUF cell array, wherein the PUF control circuit is configured to access the plurality of bit cells to pre-charge the at least two storage nodes with substantially the same voltages allowing each of the plurality of bit cell having a first metastable logical state; to determine a second logical state; and based on the determined second logical states of the plurality of bit cells, to generate a PUF signature.