Programmable Logic Reconfiguration With Synchronized Clock Completion
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing information processing systems experience waiting times when reconfiguring circuits in parallel due to mismatched clock frequencies during the processing and reconfiguration of circuits in different regions of a programmable logic circuit.
Innovation Solution
An information processing apparatus that adjusts the clock frequencies of both the processing and reconfiguration circuits to synchronize their completion times, allowing for parallel processing and reconfiguration while minimizing waiting times by dynamically adjusting the clock frequencies based on predicted completion times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If reconfiguration is performed in parallel with process execution, then productivity is improved, but waiting time increases due to clock frequency mismatch
Solution Approach 1:
The patent dynamically adjusts the clock frequency of either the process circuit or reconfiguration circuit based on real-time completion time predictions. When one circuit completes significantly earlier than the other, its clock frequency is adjusted to delay or accelerate completion, thereby minimizing idle waiting time and maximizing parallel processing efficiency.
Solution Approach 2:
The system continuously monitors the completion times of process and reconfiguration circuits, predicts future completion times based on current progress, and uses this feedback information to make real-time clock frequency adjustments. This closed-loop control ensures optimal synchronization between parallel operations.
2Speed
If clock frequency is increased to reduce waiting time, then speed is improved, but power consumption increases
Solution Approach 1:
Instead of maintaining a high fixed clock frequency, the system dynamically changes the clock frequency parameter based on actual synchronization needs. The clock frequency is adjusted to the minimum necessary level to achieve optimal parallel execution, thereby reducing unnecessary power consumption while maintaining processing speed efficiency.
3Loss of energy
If clock frequency remains unchanged, then power consumption is reduced, but waiting time increases
Solution Approach 1:
The system transitions from a static clock frequency approach to a dynamic adjustment mechanism. Clock frequency is adjusted in real-time based on the predicted completion times of parallel circuits, ensuring that power is consumed at higher levels only when necessary to reduce waiting time, rather than maintaining a constantly high frequency.
Data Source
AI summary
An information processing apparatus includes a processor connected to a programmable logic circuit. The processor is configured to: allow a first circuit reconfigured in a first region of the programmable logic circuit to execute a process; in parallel with the process of the first circuit, allow a second circuit to be reconfigured in a second region different from the first region; and adjust at least one of a clock frequency used in the process of the first circuit and a clock frequency used in reconfiguration of the second circuit so that a time point at which the process of the first circuit is completed and a time point at which the reconfiguration of the second circuit is completed will become closer to each other.