Programmable Logic Reconfiguration for Faster ML Multiplier Deployment
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Solution Overview
Problem
Large programmable logic devices face challenges in efficiently implementing machine learning applications due to the need for extensive arrays of high precision multipliers, which are costly and time-consuming to compile, leading to resource inefficiencies in area, power, and routing.
Innovation Solution
Implementing an application-aware system on a programmable logic device using a method that allows for partial reconfiguration of the device through a self-modification unit, reducing the need for full compilation by modifying configuration files to implement different overlays, thereby optimizing resource utilization and reducing compilation time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If large arrays of high precision multipliers are implemented on a target device to support machine learning applications, then the computational capability for machine learning is improved, but the area, power, and routing resources are excessively consumed
Solution Approach 1:
The patent segments the device into multiple banks, each containing a smaller array of multipliers. This allows the system to achieve the required computational capability through parallel processing across multiple segmented banks, rather than using a single large array that would consume excessive area and resources.
2Ease of manufacture
If traditional HDL compilation is used for large programmable logic devices, then the system can be implemented on the target device, but the compilation time becomes excessively long
Solution Approach 1:
The patent performs preliminary actions during device configuration by pre-computing and storing optimization information in content addressable memory (CAM). This allows the system to quickly retrieve and apply pre-computed placement and routing information during operation, avoiding the need for time-consuming compilation processes each time the device is used.
Solution Approach 2:
The patent uses content addressable memory to store and retrieve pre-computed configuration information. Instead of performing full compilation each time, the system copies and applies pre-optimized configuration data from the CAM, significantly reducing compilation time while maintaining implementation accuracy.
3Adaptability or versatility
If full compilation is performed every time a modification is needed, then the system configuration can be updated, but the compilation time and resource consumption increase unnecessarily
Solution Approach 1:
The patent applies partial action by only reconfiguring the specific portions of the device that need to be modified, rather than performing a full compilation of the entire system. The self-modification unit identifies and applies only the necessary configuration changes, significantly reducing the time and resources required for updates.
Solution Approach 2:
The system maintains pre-computed configuration information in CAM that can be quickly applied when modifications are needed. This preliminary preparation of configuration data allows for rapid updates without triggering full compilation processes, enabling frequent reconfiguration with minimal time penalty.
Data Source
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AI summary
A method for designing a system on a target device is disclosed. The system is synthesized from a register transfer level description. The system is placed on the target device. The system is routed on the target device. A configuration file is generated that reflects the synthesizing, placing, and routing of the system for programming the target device. A modification for the system is identified. The configuration file is modified to effectuate the modification for the system without changing the placing and routing of the system.