Programmable Logic Reconfiguration Without Repeating Place and Route
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Solution Overview
Problem
Large programmable logic devices face challenges in efficiently implementing machine learning applications due to the need for extensive resources and long compilation times, particularly in packing high precision multipliers, which consume area, power, and routing resources.
Innovation Solution
The implementation of an application-aware system on a programmable logic device using a self-modification unit that allows for partial reconfiguration of the device without repeating the full compilation flow, reducing the need for extensive resources and shortening compilation times by modifying configuration files to implement different overlays and LUT masks dynamically.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If large arrays of high precision multipliers are implemented on a target device to support machine learning applications, then the computational capability is improved, but the area, power, and routing resources are excessively consumed
Solution Approach 1:
The patent changes the precision parameter of multipliers from high precision to low precision. The abstract states that low precision multipliers are used to reduce resource consumption while still supporting machine learning applications. This parameter change directly addresses the contradiction by reducing area, power, and routing requirements while maintaining sufficient computational capability for the intended applications.
2Manufacturing precision
If traditional HDL compilation flow is used for large programmable logic devices, then comprehensive system optimization is achieved, but the compilation time becomes excessively long
Solution Approach 1:
The patent segments the compilation process into two distinct stages: a comprehensive HDL compilation flow for initial system optimization, and a subsequent rapid reconfiguration stage for modifications. The abstract describes how the system performs initial compilation with full optimization, then enables faster modifications by working with configuration files rather than re-running the complete HDL flow. This segmentation resolves the contradiction by separating comprehensive optimization from iterative modification needs.
Solution Approach 2:
The patent performs preliminary action by completing the comprehensive HDL compilation flow once to establish an optimized baseline system. The abstract indicates that after the initial comprehensive compilation, subsequent modifications can be made more efficiently by working with the already-compiled configuration. This preliminary comprehensive optimization eliminates the need to repeat time-consuming synthesis, placement, and routing for every modification.
3Manufacturing precision
If full compilation flow is repeated for every system modification, then complete re-optimization is achieved, but the modification time becomes excessively long
Solution Approach 1:
The patent applies partial action by performing only the necessary compilation steps for modifications rather than repeating the full compilation flow. The abstract describes how the system can make modifications by working with configuration files and performing selective re-compilation of only the affected portions, rather than re-running synthesis, placement, and routing entirely. This partial action maintains sufficient optimization quality while dramatically reducing modification time.
Data Source
AI summary
A method for designing a system on a target device is disclosed. The system is synthesized from a register transfer level description. The system is placed on the target device. The system is routed on the target device. A configuration file is generated that reflects the synthesizing, placing, and routing of the system for programming the target device. A modification for the system is identified. The configuration file is modified to effectuate the modification for the system without changing the placing and routing of the system.