Programmable Logic Region Bypass for Fault-Tolerant Programming
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Solution Overview
Problem
Existing methods for fault-tolerant programmable logic devices require additional dedicated routing circuitry and complex manufacturing infrastructure, increasing costs and complexity, while also necessitating multiple versions of programming data.
Innovation Solution
A method and system that generates bypass programming data to render faulty regions logically invisible by incorporating this data into initial programming data at specific points, eliminating the need for dedicated routing circuitry and complex infrastructure, and allowing for seamless programming of faulty regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dedicated routing circuitry is added to redirect programming data from faulty regions, then fault-tolerance is improved, but device size and cost increase
Solution Approach 1:
The patent extracts the fault-tolerance functionality from dedicated hardware circuitry and relocates it to the programming data itself. By embedding bypass information directly in the programming data structure, the system eliminates the need for separate routing circuitry while maintaining the ability to redirect around faulty regions.
Solution Approach 2:
The patent replaces the mechanical/physical routing circuitry with a data-based solution. Instead of using physical switches and routing logic in hardware, the system uses programmed bypass information in the programming data to achieve the same fault-avoidance effect through logical redirection.
2Reliability
If multiple versions of programming data are created to work around faults, then fault-tolerance is improved, but manufacturing complexity increases
Solution Approach 1:
The patent performs preliminary action by embedding bypass information in the programming data during the design phase. This pre-prepared bypass data is then automatically activated during programming based on fault location, eliminating the need for complex manufacturing decisions about which program version to use.
Solution Approach 2:
The patent creates a dynamic programming data structure that can adapt its behavior based on fault conditions. The bypass information is embedded in a way that allows the programming system to dynamically select and activate appropriate bypass paths based on the actual fault location, rather than requiring multiple static program versions.
3Productivity
If the size of programmable logic device is increased to include redundant regions, then yield is improved, but cost per usable device increases
Solution Approach 1:
The patent makes the programmable logic regions universal by designing them to serve both normal operation and bypass functions. The same logic regions can be programmed for their intended function or redirected to serve as bypass paths around faulty regions, eliminating the need for dedicated redundant hardware.
Data Source
AI summary
An apparatus for and method of programming a programmable logic device, the programmable logic device comprising a plurality of serially connected programmable logic regions. The method comprises the steps of receiving initial programming data for programming the plurality of serially connected programmable logic regions and receiving transformation data related to the presence and location of at least one faulty serially connected programmable logic region. The method also comprises the steps of generating bypass programming data which, in use, renders a serially connected programmable logic region logically invisible and generating effective programming data by incorporating, using information found in the transformation data, the bypass programming data into the initial programming data. Finally, the method comprises the step of programming the programmable logic device using the effective programming data such that the at least one faulty serially connected programmable logic region is programmed with the bypass programming data.