Programmable Logic Register Retention Across Reconfiguration
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Solution Overview
Problem
Conventional programmable logic devices (PLDs) lose data stored in volatile memory during reprogramming due to global reset signals, requiring time-consuming and complex processes to preserve data, which is not efficient for all applications.
Innovation Solution
A programmable logic device with logic blocks, registers, and routing resources that allow data transfer from logic blocks to registers before reprogramming, using a logic circuit to control data storage during reprogramming and facilitate data retrieval post-reconfiguration via a reprogrammed data path.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional PLD reprogramming is performed with global reset signal, then reprogramming can be completed, but data stored in volatile memory is lost
Solution Approach 1:
The patent segments the reset signal distribution by introducing a selective reset mechanism. Instead of applying a global reset signal to all registers, the system divides registers into two groups: those that receive the reset signal during reprogramming and those that are protected from reset. This is achieved through separate control logic that selectively enables reset functionality based on configuration bits, allowing data retention in protected registers while still enabling reprogramming.
Solution Approach 2:
The patent implements preliminary action by pre-configuring the protection status of registers before the reprogramming process begins. Configuration bits are set in advance to identify which registers should retain data, and the protection logic is prepared beforehand. When reprogramming is initiated, the protection mechanism is already in place to prevent data loss in designated registers, eliminating the need for complex post-reprogramming data recovery operations.
2Reliability
If data is preserved by reading and merging with new configuration data, then data can be maintained, but the process becomes time consuming and complex
Solution Approach 1:
The patent extracts the data protection functionality from the complex data merging process. Instead of requiring external systems to read, store, and merge data with new configuration, the invention integrates protection logic directly within the PLD. The protection logic selectively blocks reset signals to specific registers, extracting and preserving only the necessary data elements that need retention, thereby simplifying the overall process and eliminating complex external data merging operations.
Solution Approach 2:
The patent implements self-service by enabling the PLD to automatically protect and retain data in designated registers without requiring external intervention. The internal protection logic monitors reprogramming events and autonomously prevents data loss in protected registers. This self-service mechanism eliminates the need for external systems to perform complex data reading, storage, and merging operations, thereby reducing system complexity and processing time.
3Reliability
If data is preserved by reading and merging with new configuration data, then data can be maintained, but the process is time consuming
Solution Approach 1:
The patent applies preliminary action by pre-configuring protection status for registers before reprogramming begins. Configuration bits are set in advance to identify which registers should retain data, and the protection logic is prepared beforehand. When reprogramming is initiated, the protection mechanism is already in place, allowing data to be automatically retained without time-consuming external read and merge operations.
Solution Approach 2:
The patent implements self-service by enabling the PLD to automatically protect and retain data in designated registers during reprogramming without requiring external intervention. The internal protection mechanism operates autonomously, eliminating the need for time-consuming external data reading, storage, and merging processes, thereby significantly reducing reprogramming time.
Data Source
AI summary
Systems and methods provide register data retention techniques for a programmable logic device in accordance with one or more embodiments of the present invention. For example, in accordance with an embodiment, a method includes programming routing resources between programmable logic and registers of a programmable logic device to provide a data path for data prior to a reprogramming; transferring data from the programmable logic, prior to the reprogramming, to the registers via the data path to store the data within the programmable logic device during the reprogramming; reprogramming the programmable logic device, wherein the reprogramming provides a reprogrammed data path between the programmable logic and the registers of the programmable logic device; and transferring the data within the programmable logic device from the registers via the reprogrammed data path for use by the programmable logic after the reprogramming of the programmable logic device has been completed.