Logic Soft Error Rate Prediction Using Charge Node Analysis
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Solution Overview
Problem
Integrated circuits (ICs) face increasing soft error rates due to reduced charge and size of logic nodes, making them vulnerable to radiation interference, with no cost-effective method to estimate soft error rates (SER) at logic nodes, requiring time-consuming and costly physical testing.
Innovation Solution
A method to predict the logic soft error rate by determining the charge stored on logic nodes, using a database of SER data points to estimate the error rate based on technology, product type, and charge, and calculating the overall SER for the circuit by summing individual node contributions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If logic node size is decreased and charge is reduced to increase processing speeds and decrease IC size, then processing speed and IC compactness are improved, but soft error rate increases due to increased vulnerability to radiation interference
Solution Approach 1:
The patent changes the parameter of charge storage capacity at logic nodes. By reducing the charge required to represent binary states (e.g., from multiple electrons to fewer electrons or even single-electron transistors), the patent enables smaller device sizes and faster processing while managing the soft error rate through precise control of charge parameters and implementation of error detection/correction mechanisms adapted to low-charge nodes
Solution Approach 2:
The patent implements error detection and correction mechanisms beforehand to cushion against the increased soft error rate. This includes adding redundancy to logic nodes, implementing check bits, and using error-correcting codes that are specifically designed to handle the higher error rates inherent in low-charge, small-sized logic nodes
2Measurement precision
If physical testing is used to determine soft error rate at logic nodes, then measurement accuracy is improved, but time consumption and cost increase significantly
Solution Approach 1:
The patent creates a computational model that copies the physical behavior of logic nodes under radiation exposure. Instead of physically testing each node, the patent uses simulation models that replicate the charge storage characteristics, radiation interaction physics, and error propagation mechanisms, allowing accurate SER estimation without time-consuming physical experiments
Solution Approach 2:
The patent replaces the mechanical/physical testing system with a computational modeling system. By substituting physical radiation exposure and measurement with computer-based simulations that model radiation interactions, charge dynamics, and error rates, the patent achieves accurate SER prediction without the time and cost constraints of physical testing
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables accurate and efficient estimation of SER for ICs, allowing for targeted improvements to reduce error rates without the need for physical testing, thereby reducing costs and time in IC manufacturing.
Implementation Method 1
When these alpha particles strike the IC, they may create electron-hole pairs in the logic node, causing a pulse to form
Implementation Method 2
a single high energy neutron can cause a small reaction in which more than just one electron-hole pair is created
Data Source
AI summary
A process and system for estimating the soft error rate of an integrated circuit. The process involves determining the surface area of and charge stored on each logic node on the integrated circuit. Then a response curve is used to estimate the soft error rate for a logic node using the charge stored on the logic node. Different response curves exist for integrated circuits of different technologies and products. Finally, the soft error rate of the integrated circuit can be estimated using the soft error rates for each logic node.