Logic Simulation Sampling for Hardware Semantics
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional logic simulators fail to accurately replicate hardware semantics, leading to inaccuracies in debugging circuit designs due to unhandled race conditions in state elements and glitches in clock trees, which prevents effective bug localization and resolution.
Innovation Solution
The proposed solution involves simulating circuit designs by sampling signal values during the stimuli application stage and using these sampled values during the clock propagation stage to accurately handle race conditions and glitches, ensuring that logic simulation follows hardware semantics by properly managing level-sensitive and edge-triggered sequential circuit elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If conventional logic simulators are used to simulate circuit designs, then simulation speed and ease of operation are improved, but accuracy and reliability deteriorate due to unhandled race conditions and glitches
Solution Approach 1:
The patent applies preliminary action by sampling signal values at specific moments (at the beginning of the clock propagation stage, before clock glitches affect the simulation) and storing them for later use. This preliminary sampling ensures that race conditions and glitches do not compromise the accuracy of the simulation, while maintaining the ease of operation of conventional simulators.
Solution Approach 2:
The patent introduces an intermediary mechanism (signal value sampling and storage) between the stimuli application stage and the clock propagation stage. This intermediary captures signal values before clock glitches can interfere, allowing the simulator to maintain both ease of operation and high reliability by using these pre-captured values during clock propagation.
2Reliability
If logic simulators handle race conditions and glitches by following hardware semantics, then accuracy and reliability are improved, but device complexity increases
Solution Approach 1:
The patent segments the simulation process into distinct stages (stimuli application stage and clock propagation stage) with a clear boundary. By sampling signal values at the transition between stages, the patent handles race conditions and glitches without requiring complex inter-stage coordination, thus improving reliability while minimizing the increase in device complexity.
Solution Approach 2:
The patent creates copies of signal values at the end of the stimuli application stage and stores them for use during the clock propagation stage. This copying mechanism allows the simulator to follow hardware semantics and handle race conditions accurately without requiring complex real-time coordination, thereby improving reliability with minimal additional complexity.
3Measurement precision
If signal values are sampled during stimuli application stage and used during clock propagation stage, then accuracy in handling race conditions is improved, but loss of time occurs due to additional sampling and storage operations
Solution Approach 1:
The patent performs signal value sampling as a preliminary action at the end of the stimuli application stage, before the clock propagation stage begins. This timing ensures that signal values are captured with high precision before clock glitches can interfere, while the sampling operation itself is efficiently integrated into the existing simulation workflow to minimize time loss.
Solution Approach 2:
The patent implements a self-service mechanism where the simulator automatically samples and stores signal values at the appropriate stage transition without requiring external intervention or complex coordination. This self-service approach ensures precise capture of signal values while minimizing the time overhead by integrating the sampling operation into the natural flow of the simulation process.
Data Source
AI summary
Some embodiments of the present invention provide techniques and systems for simulating a circuit design so that the simulation follows hardware semantics. Specifically, some embodiments ensure that the simulation follows hardware semantics by properly handling race conditions in state elements and/or glitches in clock trees that can occur during logic simulation. Each logic simulation cycle can include two stages: a stimuli application stage in which the system evaluates signal values of the circuit design which do not depend on a clock signal, and a clock propagation stage in which the system evaluates signal values that depend on a clock signal. Some embodiments of the present invention sample signal values during the stimuli application stage, and use the sampled signal values during the clock propagation stage to handle race conditions in state elements and/or glitches in clock trees that may occur during logic simulation.