Logic Simulation Verification System for Signal Contention Analysis
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Solution Overview
Problem
Logic simulation systems face challenges in achieving consistent results due to signal contention states caused by read-write (RW) and write-write (WW) hazards, leading to differing simulation outcomes from the same input information.
Innovation Solution
A logic simulation verification system that designates reference signals and calculates change timing possibilities to determine matching times for signals across different circuits, outputting messages to prevent signal contention by modifying the input information data to ensure consistent simulation results.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If logic simulation is executed using input information data including library, circuit description, and test bench file, then simulation results can be obtained, but signal contention states occur causing inconsistent simulation results from the same input information
Solution Approach 1:
The patent performs preliminary static analysis before logic simulation to identify potential signal contention states (RW and WW hazards) by calculating change timing possibilities of signals. This advance detection allows modification of input information data to prevent contention, ensuring consistent simulation results without relying on complex runtime analysis during simulation execution.
2Reliability
If logic simulator analyzes signal contention state to ensure consistent results, then simulation reliability improves, but analysis time increases
Solution Approach 1:
The patent extracts and separates the signal contention analysis from the main logic simulation process by performing static analysis independently on the input information data. This extraction allows contention detection to occur in advance without adding time overhead to the actual simulation execution, as the analysis results are used to modify the input data before simulation begins.
3Productivity
If static analysis is performed to detect signal contention without logic simulator, then analysis speed improves, but detection precision may be affected
Solution Approach 1:
The patent replaces the mechanical simulation execution process with a static analysis approach that uses timing information and signal change possibility calculations. By substituting dynamic simulation with static timing analysis, the system achieves faster analysis speed while maintaining sufficient detection precision for identifying RW and WW hazards through mathematical timing comparisons rather than iterative simulation.
Data Source
AI summary
A logic simulation verification system designates a change timing designation unit configured to designate a reference signal and a change timing and calculate a first time for which there is a possibility that a first signal to be assigned to a variable described in a library, a circuit description, and a test bench is changed in accordance with the reference signal. The system calculates a second time for which there is a possibility that a second signal assigned a variable described in the library, the circuit description, and the test bench will be checked in accordance the reference signal and then determines whether different circuits for which first signals are the same have first times that match. The system also determines whether a first time and a second time match with each other when a first signal of one circuit and a second signal of another circuit are the same.