Logic Simulator Memory Loading Using Accessed Address Subsets
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Solution Overview
Problem
Current methods for loading memory onto logic simulators are time-consuming, especially when dealing with large and complex applications, as they require loading the entire memory address space, which prolongs the simulation time.
Innovation Solution
The method involves identifying and selectively loading only the subsets of memory that will be accessed by the program during execution on the logic simulator, using memory addresses traced during program execution on a computer system to create contiguous address ranges, thereby reducing the memory load time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the entire memory address space is loaded onto the logic simulator, then the simulation completeness is ensured, but the memory load time increases significantly
Solution Approach 1:
The patent divides the entire memory address space into multiple segments or subsets based on actual program access patterns. Instead of loading all memory, only the relevant segments that contain addresses actually accessed by the program are identified and loaded onto the logic simulator, thereby reducing load time while maintaining simulation accuracy for the accessed portions.
Solution Approach 2:
The patent extracts and identifies the specific subsets of memory addresses that are actually accessed by the program during execution. By using static analysis or execution traces from a reference run, the method extracts only the necessary memory portions and loads them onto the logic simulator, eliminating the need to load unnecessary memory segments.
2Adaptability or versatility
If larger and more complex applications are simulated, then the application capability is improved, but the memory load time increases
Solution Approach 1:
The patent performs preliminary analysis of the program's memory access patterns before actual simulation execution. By conducting static analysis or using execution traces in advance, the method pre-identifies the memory subsets that will be accessed, allowing the logic simulator to be configured with only the necessary memory portions before the actual simulation begins, thus reducing load time for complex applications.
Solution Approach 2:
The patent applies partial action by loading only the necessary subset of memory required for the specific program being simulated, rather than loading the complete memory space. This partial loading approach is sufficient for maintaining simulation accuracy while dramatically reducing the time required to prepare and load memory for complex applications.
Data Source
AI summary
A method, system and computer program product are disclosed for reducing the memory load time for logic simulator. In an embodiment, the method comprises identifying a memory for a program, and selectively loading onto a logic simulator parts of the memory that are pre-determined as parts of the memory that will be accessed by the program when the program is executed on the simulator. In an embodiment, the selectively loading onto a logic simulator parts of the memory includes pre-determining subsets of the memory that will be accessed by the program when the program is executed on the simulator, and loading the pre-determined subsets of the memory on the simulator. In an embodiment, the pre-determining subsets of the memory includes using addresses of the memory that are accessed by the program when the program is executed on a computer system, to create the pre-determined subsets of the memory.