Logic Region Sidewall Spacer for Memory Fill Voids
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Solution Overview
Problem
The formation of sidewall spacers in integrated circuit manufacturing narrows the lateral spaces between adjacent select gate electrodes, leading to high aspect ratios and voids in inter-layer dielectric material, which can result in defects such as unwanted shorting or bridging during subsequent manufacturing processes.
Innovation Solution
The implementation of an integrated circuit design where a sidewall spacer is only formed alongside the logic device, not the memory cell structure, allowing for a broader inter-layer dielectric fill-in space and reducing void formation by ensuring the contact etch stop layer directly contacts the spacer within the logic region and not the memory cell structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If sidewall spacers are formed alongside memory cell structures, then device density is improved, but lateral spaces between adjacent select gate electrodes are narrowed leading to high aspect ratios and voids in inter-layer dielectric material
Solution Approach 1:
The patent divides the substrate into distinct memory regions and logic regions, with sidewall spacers formed only in logic regions. This segmentation allows different structures to coexist: memory regions maintain high density without spacers, while logic regions have spacers for proper device operation, thereby resolving the contradiction between density and fill quality
Solution Approach 2:
The patent applies sidewall spacers selectively only to logic devices and not to memory cell structures. This local differentiation allows the inter-layer dielectric material to be properly deposited in memory regions (avoiding voids) while still providing necessary spacer structures in logic regions, thus improving overall manufacturing precision without sacrificing device density
2Reliability
If sidewall spacers are formed in logic regions, then device operation is enabled, but lateral spaces are reduced causing high aspect ratios that lead to voids and defects
Solution Approach 1:
By segmenting the substrate into memory and logic regions with different spacer configurations, the patent enables logic devices to operate reliably (with spacers) while preventing void formation in memory regions (without spacers), thus eliminating harmful defects while maintaining device operation
Solution Approach 2:
The selective formation of sidewall spacers acts as an intermediary solution that mediates between the need for device operation (requiring spacers in logic regions) and the need to prevent voids (requiring no spacers in memory regions), allowing both requirements to be satisfied simultaneously through regional differentiation
Data Source
AI summary
Various embodiments of the present application are directed to an IC, and associated forming methods. In some embodiments, the IC comprises a memory region and a logic region integrated in a substrate. A memory cell structure is disposed on the memory region. A logic device is disposed on the logic region having a logic gate electrode separated from the substrate by a logic gate dielectric. A sidewall spacer is disposed along a sidewall surface of the logic gate electrode. A contact etch stop layer (CESL) is disposed along an upper surface of the substrate, extending upwardly along and in direct contact with sidewall surfaces of the pair of select gate electrodes within the memory region, and extending upwardly along the sidewall spacer within the logic region.