Reconfigurable Logic Storage Interface for Low-Latency Data Transfer
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Solution Overview
Problem
Current storage systems face challenges in minimizing input and output delays due to the inefficiencies in data transmission and reception processes, particularly when using switches that transmit signals through multiple layers, which can hinder processing speed and performance.
Innovation Solution
Incorporating a reconfigurable logic chip with a retimer that adjusts input signals and an operation circuit to perform specific functions, allowing for direct communication between the storage device and the host via a physical layer, thereby reducing delays and enhancing data transmission speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a switch is used to transmit signals through multiple layers, then device complexity is reduced, but input and output delay increases
Solution Approach 1:
The patent extracts the signal transmission function from the switch and places it directly in the storage device through a retimer component. This removes the intermediate switching layer, allowing signals to be transmitted directly without passing through multiple switch layers, thereby reducing input and output delay while maintaining manageable device complexity through dedicated hardware components.
Solution Approach 2:
The patent introduces a retimer as an intermediary component within the storage device that directly handles signal transmission. This retimer acts as a dedicated mediator for signal timing and transmission, replacing the general-purpose switch architecture. The retimer minimizes signal processing delay by being specifically designed for direct signal transmission between the storage device and host, rather than routing through multiple switch layers.
2Speed
If a reconfigurable logic chip with retimer is used for direct communication, then data transmission speed is improved, but device complexity increases
Solution Approach 1:
The patent merges the retimer and operation circuit into a single reconfigurable logic chip that is directly integrated with the storage device. This consolidation allows high-speed direct communication between the storage device and host while managing complexity through integration. The merged architecture enables the storage device to perform specialized operations (encryption, compression, etc.) at high speed without requiring separate complex external components.
Solution Approach 2:
The patent uses a reconfigurable logic chip that can change its operational parameters and configuration based on different applications. This allows the same hardware infrastructure to adapt to various data transmission requirements and operation types, achieving high transmission speed for different workloads without proportionally increasing device complexity. The reconfigurability enables efficient resource utilization across multiple scenarios.
Data Source
AI summary
A storage device set is provided. The storage device set includes a reconfigurable logic chip and a storage device. The logic chip includes a retimer configured to generate an output signal by adjusting an input signal received from an external device; and an operation circuit configured to perform an operation function. The storage device includes: a first port connected to the retimer; a second port connected to the operation circuit; and a controller configured to control data transmission and reception via the first port and the second port.