Logic Synthesis Cell Selection for Load Sensitivity
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Solution Overview
Problem
As integrated circuit designs approach 28 and 20 nm technology nodes, circuit behavior becomes increasingly unpredictable due to sensitivity to parasitic loads and environmental variations, leading to performance and design rule compliance issues.
Innovation Solution
A method for synthesizing circuit designs that selects standard cells based on sensitivity to load capacitance, using a sensitivity database to identify optimal cell combinations and buffer placement to reduce variability, ensuring robustness against environmental changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional logic synthesis is used at 28nm and 20nm nodes, then circuit density and integration are improved, but circuit behavior becomes unpredictable due to sensitivity to parasitic loads and environmental variations
Solution Approach 1:
The patent applies parameter changes by modifying the cell selection criteria to include sensitivity to load capacitance as a key parameter. The synthesis tool evaluates multiple candidate cells and selects based on both performance and sensitivity characteristics, changing the optimization parameters from traditional metrics alone to include environmental robustness metrics.
Solution Approach 2:
The patent introduces an intermediary sensitivity database that mediates between the logic synthesis process and the physical implementation. This database provides sensitivity information about library cells to the synthesis tool, enabling it to make informed selections that account for parasitic load effects without requiring complete physical design knowledge at the synthesis stage.
2Adaptability or versatility
If multiple library cells are available for each functional block, then optimization flexibility is improved, but selection complexity increases due to multiple factors to consider
Solution Approach 1:
The patent implements feedback by having the synthesis tool query the sensitivity database for characteristics of candidate cells and use this information to guide the selection process. The tool evaluates multiple cells, compares their sensitivity profiles against design requirements, and selects the most appropriate cell, providing feedback loops that simplify the complexity of having multiple options.
Solution Approach 2:
The sensitivity database is prepared in advance with pre-characterized sensitivity information for all library cells. This preliminary action allows the synthesis tool to quickly access and compare cell characteristics during the selection process, avoiding the need to perform complex sensitivity analyses in real-time and reducing selection complexity.
Data Source
AI summary
Roughly described, a method for synthesizing a circuit design from a logic design includes developing candidate solutions for a particular signal path, a first candidate solution identifying a first library cells followed immediately downstream thereof by a first set of zero or more buffers, and a second candidate solution identifying a second library cell followed immediately downstream thereof by a second set of zero or more buffers, the first library cell and first set of buffers in combination being different from the second library cell and second set of buffers in combination. The computer system selects among the candidate solutions at least in part in dependence upon sensitivity of the solution to load capacitance in the particular path, and stores the selected solution in the storage for subsequent use in further developing and fabricating an integrated circuit device.