Logic Tile Clock Architecture for Minimal Skew Synchronization
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Solution Overview
Problem
Current integrated circuit technologies face challenges in distributing and synchronizing clock signals between logic tiles with minimal skew, which affects the orderly operation and communication within and between logic tiles, particularly in FPGAs and other programmable logic circuits.
Innovation Solution
The implementation of clock distribution and transmission circuitry within logic tiles, utilizing u-turn circuits and multiplexers to generate and distribute tile clocks with programmable skew, ensuring synchronization and zero or minimal phase difference across the array of logic tiles, thereby facilitating efficient operation and communication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If clock signals are distributed across logic tiles using conventional methods, then the circuit can operate, but clock skew between tiles increases
Solution Approach 1:
The patent divides the clock distribution system into multiple independent clock trees, each serving specific logic tiles. Each clock tree is configured to provide locally optimized clock signals, reducing the impact of global skew on individual tiles. This segmentation allows different regions of the circuit to have tailored clock distribution paths.
Solution Approach 2:
The patent implements local clock generation and distribution within each logic tile or group of tiles, rather than relying on a single global clock distribution network. This allows each local clock network to be optimized for its specific region, minimizing local skew and improving synchronization accuracy within each tile.
2Device complexity
If clock distribution network is simplified, then device complexity is reduced, but clock skew control capability deteriorates
Solution Approach 1:
The clock distribution network is segmented into multiple manageable clock trees, each with its own configuration capabilities. This segmentation reduces the complexity of controlling any single clock network while maintaining overall skew control through localized optimization of each segment.
Solution Approach 2:
The patent employs dynamically configurable clock trees that can be programmed and adjusted after fabrication. This dynamic configurability allows the clock distribution network to adapt to different operating conditions and tile configurations, providing skew control flexibility without requiring a complex fixed infrastructure.
3Manufacturing precision
If multiple clock trees are configured per logic tile, then clock skew is minimized, but device complexity increases
Solution Approach 1:
The patent divides the clock distribution function into multiple independent clock trees that can be selectively activated. Each clock tree is optimized for specific spatial regions, allowing the system to achieve low skew in local areas without requiring all tiles to implement the full complexity of multiple configured trees simultaneously.
Data Source
AI summary
An integrated circuit comprising an array of logic tiles, arranged in an array of rows and columns. The array of logic tiles includes a first logic tile to receive a first external clock signal wherein each logic tile of a first plurality of logic tiles generates the tile clock using (i) the first external clock signal or (ii) a delayed version thereof from one of the plurality of output clock paths of a logic tile in the first plurality, and a second logic tile to receive a second external clock signal wherein each logic tile of a second plurality of logic tiles generates the tile clock using (i) the second external clock signal or (ii) a delayed version thereof from one of the plurality of output clock paths of a logic tile in the second plurality, wherein the first and second external clock signals are the same clock signals.