Logic Tile Switch Network With Hierarchical Mesh Routing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current integrated circuits face limitations in efficiently interconnecting computing elements due to rigid radix-based switch matrix architectures, which restrict flexibility and performance in terms of operating speed, switching time, and resource utilization.
Innovation Solution
The implementation of a mixed-radix and mixed-mode switch matrix interconnect architecture, where computing elements are associated with switch matrices configured in multiple radices and network types, such as hierarchical and mesh networks, to enhance interconnectivity and resource allocation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a rigid radix-based switch matrix architecture is used, then the structure is simple and easy to manufacture, but the flexibility and performance in terms of operating speed, switching time, and resource utilization are limited
Solution Approach 1:
The patent implements a reconfigurable switch matrix architecture where the radix (base) of the interconnect network can be dynamically changed. Switch matrices can be configured to operate in different radix modes (e.g., radix-2, radix-4, radix-8) depending on the computational requirements, allowing the system to adapt its interconnect topology to match the data flow patterns of different algorithms or operational modes, thereby resolving the contradiction between architectural simplicity and operational flexibility
Solution Approach 2:
The patent changes the structural parameter of the switch matrix from a fixed radix to a variable radix configuration. By allowing the radix parameter to be adjusted based on computational needs, the system can optimize resource utilization and switching performance for different workloads while maintaining a unified hardware structure, thus improving adaptability without proportionally increasing complexity
2Productivity
If a single radix configuration is used for all switch matrices, then the device complexity is reduced, but the path diversity and routing efficiency are limited
Solution Approach 1:
The patent divides the interconnect network into multiple stages of switch matrices, where each stage can be independently configured with different radix values. This segmentation allows different portions of the network to be optimized for different routing requirements, enabling efficient path selection and load distribution across multiple configurable stages, thereby improving routing efficiency while managing complexity through modular design
3Adaptability or versatility
If more switch matrix stages are added to improve path diversity, then the routing flexibility increases, but the network latency and switching time increase
Solution Approach 1:
The patent employs dynamic radix configuration across multiple switch matrix stages, where the radix of each stage can be adjusted in real-time based on traffic patterns and routing requirements. This dynamic adaptation allows the network to optimize the number of stages actively used for different computational tasks, providing high path diversity when needed while minimizing latency by using fewer stages when possible, thus resolving the time-diversity tradeoff
Data Source
AI summary
An integrated circuit comprising a plurality of logic tiles, wherein each logic tile (i) is physically adjacent to at least one other logic tile of the plurality and (ii) includes a configurable switch interconnect network including a plurality of switches electrically interconnected and arranged into a plurality of switch matrices, wherein the plurality of switch matrices are arranged into a plurality of stages including: (a) at least two of the stages which is configured in a hierarchical network, and (b) a mesh stage, wherein each switch matrix of the mesh stage includes an output that is directly connected to an input of a plurality of different switch matrices of the mesh stage and wherein the mesh stage of switch matrices of each logic tile is directly connected to the mesh stage of switch matrices of at least one other logic tile of the plurality of the logic tiles.