Configurable Logic Tile Interconnects With Direct Offset Routing
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Solution Overview
Problem
Existing configurable IC architectures are inefficient due to redundant connections and high costs associated with transistor switching logic, leading to suboptimal interconnectivity between computational tiles.
Innovation Solution
The implementation of a configurable IC with direct offset connections between tiles, utilizing wire segments across multiple wiring layers and vias, along with buffer circuits to enhance interconnectivity and reduce redundant pathways.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If transistor switching logic is used for interconnect circuits, then configurable functionality is achieved, but device complexity and cost increase
Solution Approach 1:
The patent extracts the switching function from transistor-based logic and implements it using multiplexer circuits with configuration bits stored in SRAM cells. This separates the configurable control logic from the interconnect wiring, reducing overall device complexity while maintaining adaptability.
Solution Approach 2:
The patent introduces multiplexer circuits as intermediary elements between input and output signals. These multiplexers are controlled by configuration bits that act as mediators, enabling configurable connectivity without requiring complex transistor switching logic throughout the entire interconnect fabric.
2Adaptability or versatility
If redundant connections are provided between tiles, then interconnectivity is improved, but device complexity and cost increase
Solution Approach 1:
The patent implements universal interconnect lines that can serve multiple functions and connect to multiple tiles. Each interconnect line is designed to be configurable through multiplexers, allowing a single physical connection to fulfill multiple routing roles depending on the configuration bits, thereby eliminating the need for redundant dedicated connections.
Solution Approach 2:
The patent makes the interconnect fabric dynamic and reconfigurable through configuration bits stored in SRAM cells. The connectivity topology can be changed at runtime by modifying the configuration data, allowing the same physical structure to adapt to different interconnection requirements without requiring redundant fixed connections.
Data Source
AI summary
An integrated circuit (IC) is disclosed that includes a set of configurable logic circuits. Each configurable logic circuit configurably performs a set of functions. A particular configurable circuit receives configuration data defining a function for the particular configurable circuit. In some embodiments, one configuration of a configurable circuit is to add two input signals received by the configurable circuit. Also, in some embodiments, one configuration is to subtract two input signals received by a configurable circuit. In some such embodiments, each configurable logic circuit receives a first input signal, a second input signal, and a carry input signal and generates a propagate and generate signal for the add or subtract operation based on the inputs to the configurable circuit and the configuration of the configurable circuit.