Logic-on-Top Power Delivery Through TSV Memory Stacks
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Solution Overview
Problem
Thermal challenges and power delivery issues arise in semiconductor systems with a Logic-on-Top (LoT) configuration, where a high-power logic component is placed over memory dies, leading to heat trapping and increased lateral distance for power conveyance.
Innovation Solution
Implementing a two-dimensional pattern of power delivery conductors, including through-substrate vias (TSVs), that bypass circuitry within the stack to provide direct power distribution to the logic component, combined with redistribution components for efficient power delivery.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a Logic-on-Top configuration is used to integrate logic component over memory dies, then processing density and integration are improved, but thermal management deteriorates due to heat trapping
Solution Approach 1:
The patent transitions from lateral power delivery (2D plane) to vertical power delivery through the substrate (3D space). Through-substrate vias conductors extend the power delivery path into the vertical dimension, bypassing the lateral routing through memory dies and directly connecting to the logic component, thereby reducing the power delivery path length and improving thermal management.
Solution Approach 2:
Through-substrate vias conductors act as intermediary elements that facilitate direct power delivery from the substrate to the logic component. These vias serve as conduits that penetrate the substrate, providing a dedicated power delivery path that bypasses the memory die circuitry and reduces thermal interference.
2Productivity
If logic component is placed over memory dies, then integration is improved, but power delivery path length increases due to lateral distance
Solution Approach 1:
The invention utilizes the vertical dimension by implementing through-substrate vias conductors that extend perpendicular to the substrate plane. This allows power to be delivered directly from the substrate through the vias to the logic component, bypassing the lateral routing path through memory dies and significantly reducing the power delivery path length.
Solution Approach 2:
The power delivery system is segmented into dedicated vertical pathways (through-substrate vias) separate from the lateral signal routing through memory dies. This segmentation creates independent power delivery channels that optimize the power path by eliminating unnecessary lateral traversal through the memory array.
3Ease of manufacture
If power is delivered laterally through memory dies, then existing substrate structure is used, but power consumption increases due to longer delivery path
Solution Approach 1:
The patent introduces vertical through-substrate vias conductors that penetrate the substrate, creating a third-dimensional power delivery path. This vertical pathway significantly shortens the power delivery distance compared to lateral routing through memory dies, thereby reducing I2R losses and overall power consumption while maintaining compatibility with existing substrate structures.
Solution Approach 2:
The invention changes the geometric parameters of the power delivery path by transitioning from lateral to vertical orientation. Through-substrate vias provide direct vertical access to the logic component, reducing the path length parameter and consequently lowering the power consumption associated with power delivery.
Data Source
AI summary
Methods, systems, and devices for pass-through power delivery for logic-on-top semiconductor systems are described. A semiconductor system may be configured with a two-dimensional pattern of power delivery conductors that pass through semiconductor components of a stack (e.g., through one or more memory stacks), providing a more-distributed delivery of power to a logic component bonded with the stack. The power delivery conductors may include through-substrate vias that bypass circuitry of the stack, and thus may be allocated for providing power to the logic component. Such techniques may be combined with a redistribution component, such as a package substrate or interposer (e.g., opposite the logic component in the heterogeneous stack), which may include redistribution conductors that convert from relatively fewer interconnections at a surface of the semiconductor system (e.g., for solder interconnection) to relatively more interconnections at a surface bonded with the stack (e.g., for hybrid bonding interconnection).