Logic Transistor Shared-Node Layout for Higher Integration
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor devices face challenges in increasing integration density due to the complexity and area occupied by interconnection structures, especially when reducing linewidths of patterns.
Innovation Solution
A layout design method that divides a logic transistor into multiple unit transistors, connected in series and parallel, to simplify the interconnection structure and reduce the area occupied by connections, thereby increasing integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of transistors is increased to improve integration density, then the interconnection structure becomes more complex and occupies more area
Solution Approach 1:
The logic transistor is divided into multiple sub-transistors (first sub-transistor, second sub-transistor, etc.) that are connected in series. Each sub-transistor has its own source and drain regions, but they share a common node region. This segmentation allows the interconnection structure to be simplified because adjacent sub-transistors share common source/drain regions, reducing the number of separate interconnection lines needed.
2Quantity of substance
If the number of transistors is increased to improve integration density, then the area occupied by interconnection structures increases
Solution Approach 1:
Adjacent sub-transistors share common source and drain regions (the common node region). The first sub-transistor shares a drain region with the second sub-transistor's source region, and this pattern continues through the series connection. This merging of regions eliminates the need for separate interconnection structures between each transistor, significantly reducing the total area occupied by interconnections.
3Quantity of substance
If linewidths are reduced to increase integration density, then manufacturing precision requirements increase
Solution Approach 1:
Instead of increasing integration density solely by reducing linewidths in the horizontal dimension, the patent uses vertical stacking of multiple sub-transistors in series and shares common source/drain regions. This approach increases effective transistor density without requiring proportionally smaller linewidths, thereby reducing the stringent manufacturing precision requirements that would otherwise be needed.
Data Source
AI summary
A semiconductor device, including: a first substrate; a first device isolation portion in the first substrate around a first active region extending in a first direction; a plurality of sub-transistors connected to form a logic transistor; and a common node region at a center of the first active region, wherein the common node region is shared by the plurality of sub-transistors, wherein each sub-transistor includes: at least three gate electrodes which cross the first active region in a second direction intersecting the first direction; and a plurality of source regions and a plurality of drain regions disposed in the first active region adjacent to sidewalls of the at least three gate electrodes, wherein the plurality of source regions are alternatingly arranged with the plurality of drain regions in the first direction.