Logic Tree Analysis for Digital Driver Contention Detection
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Solution Overview
Problem
Existing methods, such as simulation software like SPICE, often fail to detect design errors in complex electronic circuits, particularly floating FET gates and unintended contention, which can lead to unpredictable behavior, excess current consumption, and device failure in integrated circuits.
Innovation Solution
The development of software-based methods using expanding logic tree analysis to identify floating gates and contention by analyzing digital drivers, creating a logical tree representation of predecessor circuit portions to determine if they create pull-up or pull-down paths to power or ground nets, thereby detecting potential contention configurations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If simulation software like SPICE is used to verify circuit function, then circuit simulation capability is provided, but design errors such as floating FET gates and unintended contention remain undetected
Solution Approach 1:
The patent replaces time-domain simulation (SPICE) with topology-based logical analysis. Instead of simulating circuit behavior over time, the system performs static topological analysis of the circuit graph to detect structural errors like floating gates and contention. This substitution of analysis methodology enables detection of design errors that simulation misses.
Solution Approach 2:
The patent performs preliminary topological analysis of the circuit design before simulation or fabrication. By analyzing the circuit topology in advance to identify floating gates and contention conditions, the system catches errors early in the design process, preventing them from manifesting as harder-to-detect issues during simulation or operation.
2Reliability
If peer review inspection is performed on circuit schematics, then circuit design errors can be discovered, but the process becomes increasingly complex and time-consuming as circuit size grows
Solution Approach 1:
The patent implements automated self-verification of circuit designs. The system automatically analyzes the circuit topology, identifies floating gates and contention conditions, and generates verification reports without requiring manual peer review. This automation allows the circuit to essentially verify itself, scaling efficiently regardless of circuit size.
Solution Approach 2:
The patent replaces manual peer review inspection with automated computer-based topological analysis. The system uses algorithmic methods to systematically examine circuit connections, gate terminals, and signal paths, substituting human inspection with automated computational verification that scales with circuit complexity.
3Productivity
If automated netlist analysis is performed to detect design errors, then verification speed increases, but detection accuracy for subtle errors like floating gates decreases
Solution Approach 1:
The patent segments the verification process into distinct analysis phases: (1) identification of digital drivers and their outputs, (2) detection of contention conditions, and (3) verification of gate terminal connections. This segmentation allows each phase to focus on specific error types with dedicated algorithms, maintaining high accuracy while achieving automated verification speed.
Solution Approach 2:
The patent applies different analysis depths and methods to different circuit elements based on their local characteristics. Critical elements like gate terminals and output nodes receive specialized attention with targeted verification algorithms, while less critical elements are analyzed with simpler methods. This localized quality approach maintains high detection accuracy for subtle errors while preserving overall verification efficiency.
Data Source
AI summary
Software method to identify presence of multiple digital drivers disposed in a manner that creates multiple conflicting current paths in complex electronic circuit designs. Digital drivers are analyzed by expanding backwards to build a logical tree representation of the previous predecessor circuit portions that drive the digital driver's state. The previous level of predecessor circuit node states earlier in the circuit are checked to see if they simultaneously create pull up paths to power nets and pull down paths to ground nets, thus logically determining if a contention configuration is possible. This back-trace analysis is then repeated for the next previous level of predecessor circuit portions, further seeking logical contention issues within the expanding logic tree. This is continued until either no predecessor circuit portion that causes contention is found, or until a portion that does cause logical contention is found, in which case the contention digital drivers are reported.