Logic Verification Model Using Address Conversion
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Solution Overview
Problem
The increasing complexity of computer systems due to finer semiconductor development makes it difficult to verify logic circuits using existing simulation methods, as large-scale simulators are costly and may not accommodate all configurations, leading to incomplete verification models and increased development steps.
Innovation Solution
A logic verifying apparatus with a reduced number of controllers and processors that uses address conversion to simulate access to memories, allowing for verification models to be created that accommodate all controller combinations, reducing the need for large-capacity simulators and simplifying the verification process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a large-scale simulator is used to create a verification model with the entire configuration of the computer system, then the verification completeness is improved, but the cost and device complexity increase significantly
Solution Approach 1:
The patent divides the computer system into multiple domains, each managed by a domain controller. Instead of simulating the entire system at once, the verification model is segmented into smaller domain-specific models that can be verified independently and then integrated. This reduces the complexity of any single verification model while maintaining overall verification completeness.
Solution Approach 2:
The patent creates a universal interface model that can represent multiple different controllers and memory configurations through a standardized interface. This allows a single verification model to verify multiple controller combinations without requiring separate models for each configuration, reducing device complexity while maintaining verification completeness.
2Reliability
If the verification model includes all controller combinations to cover every access pattern, then the verification coverage is improved, but the number of required controllers and memories increases
Solution Approach 1:
The patent uses interface models that copy and represent the behavior of multiple different controllers through a standardized interface. Instead of including physical copies of all controllers in the verification model, the interface models simulate their access patterns, reducing the quantity of controllers needed while maintaining verification coverage.
Solution Approach 2:
The patent verifies multiple controller combinations by changing parameters in the interface model configuration rather than physically adding controllers. The same verification model can be reused with different parameter settings to verify different controller combinations, reducing the number of controllers needed while maintaining comprehensive verification coverage.
3Reliability
If a verification model with the maximum configuration is created, then all access patterns can be verified, but the cost of the simulator increases
Solution Approach 1:
The patent segments the verification process into domain-specific verification models that can be executed on smaller, more affordable simulators. Each domain model verifies specific access patterns relevant to that domain, eliminating the need for an expensive large-scale simulator while maintaining comprehensive verification capability.
Solution Approach 2:
The patent designs universal interface models that can represent multiple controller types and configurations through standardized interfaces. This multi-functionality allows a single verification model to verify diverse access patterns without requiring a large-scale simulator, reducing device complexity and cost while maintaining verification comprehensiveness.
Data Source
AI summary
A logic verifying apparatus includes a second processor corresponding to a first processor to be verified; and one or more second controllers corresponding to first controllers to be verified, the number of which is less than that of the first controllers, control a second access to a memory, the access being made by the second processor, the second processor and the second controllers serving as elements in the verification model. The second processor includes a storing unit that stores information that assigns one or more of the second controllers that is to be used as the verification model; and a converting unit that converts a first address into a second address, the first address indicating an entity that the second processor is to access through the one second controller assigned by the information stored in the storing unit such that the second processor access to the memory.