Multi-Core Logic Verification Chip Architecture
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Solution Overview
Problem
Current logic verification technologies, such as FPGA-based systems, face scalability issues, high costs, and inefficiencies due to slow performance, especially when simulating complex chip logic, and are not commercially available for outside users.
Innovation Solution
A multi-core chip architecture with a logic verification core (LVC) chip that translates input logic designs into primitive operations, using a compiler and synthesizer to generate executable code for the LVC chip, which includes a network of interconnected cores with shared memory, optimizing simulation speed and resource usage through dataflow representation and pipelined instructions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If FPGA-based systems are used for logic verification, then logic simulation can be performed, but the performance is slow and scalability is poor
Solution Approach 1:
The patent segments the logic verification system into multiple independent cores that can operate in parallel. Each core handles a portion of the logic simulation independently, allowing the system to scale by adding more cores. This segmentation resolves the contradiction by enabling faster simulation through parallel processing while maintaining manageable complexity at the core level.
Solution Approach 2:
The patent replaces traditional FPGA-based mechanical/electronic simulation systems with a software-based virtualization approach. By using software to emulate logic circuits and enable parallel execution, the system achieves higher performance without the physical constraints and complexity of FPGA hardware configurations.
2Productivity
If dedicated ASIC systems are developed for logic simulation, then performance improves, but development cost and complexity increase significantly
Solution Approach 1:
The patent creates a universal logic verification platform that can simulate multiple different logic circuits and designs using the same hardware infrastructure. The virtualized environment allows a single system to perform the functions of multiple dedicated ASIC systems, improving productivity while reducing development costs through shared resources.
Solution Approach 2:
The patent uses software-based copying of logic circuit functionality rather than physical ASIC fabrication. Virtual copies of logic circuits can be created, modified, and executed on standard hardware, achieving dedicated-ASIC-level efficiency without the high costs of custom chip development and manufacturing.
3Adaptability or versatility
If PC clusters are used for simulation, then resource flexibility is maintained, but performance is limited due to cache locality and communication overhead
Solution Approach 1:
The patent merges the advantages of dedicated hardware performance with the flexibility of software-based systems. By combining parallel processing capabilities with virtualized logic simulation on standard multi-core processors, the system achieves high performance while maintaining the adaptability and flexibility of software environments, eliminating the need for specialized hardware communication channels.
Data Source
AI summary
Methods and systems for simulating logic may translate logic design into executable code for a multi-processor based parallel logic simulation device. A system may implement one or more parallel execution methods, which may include IPMD, MPMD, and/or DDMT.