Logic Verification Apparatus Preventing Indeterminate Value Erasure
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Solution Overview
Problem
Existing logic verification technologies fail to prevent unintentional erasure of indeterminate values in Verilog HDL-based logic circuits, leading to overlooked errors during logic synthesis and potential circuit failures.
Innovation Solution
A logic verification apparatus that simulates logic functions, replaces indeterminate values with symbols, and propagates these symbols through the circuit, preventing their unintentional erasure and allowing for accurate identification of their source.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If logic verification is performed using conventional methods, then verification process is simple, but indeterminate values are unintentionally erased and users cannot detect errors
Solution Approach 1:
The patent introduces a symbol (e.g., '?') as an intermediary to represent indeterminate values during simulation. This symbol acts as a mediator between the indeterminate value and the verification process, allowing the system to track and detect where indeterminate values originate without complicating the entire verification apparatus. The symbol replaces the indeterminate value in the simulation result and propagates through the circuit to identify the source.
Solution Approach 2:
The patent uses visual differentiation (analogous to color changes) by introducing a special symbol '?' to mark indeterminate values in the simulation output. This visual marker allows users to easily identify and detect indeterminate values in the verification results, making them stand out from normal deterministic values without requiring complex analysis tools.
2Productivity
If indeterminate values are treated as Don't Care in logic synthesis, then synthesis process is simplified, but users overlook abnormal indeterminate values and must re-execute verification
Solution Approach 1:
The patent performs preliminary detection of indeterminate values during the simulation phase before logic synthesis occurs. By using the symbol '?' to mark and track indeterminate values throughout the circuit simulation, the system identifies problematic areas in advance. This preliminary action allows users to address indeterminate value issues before they cause problems during synthesis and verification re-execution, improving overall productivity.
3Speed
If branching statements are executed without checking indeterminate values, then simulation speed is maintained, but indeterminate values are unintentionally erased
Solution Approach 1:
The simulation apparatus automatically handles indeterminate values by replacing them with the symbol '?' and propagating this symbol through subsequent operations. The system serves itself by automatically detecting and marking indeterminate values without requiring user intervention or complex additional processing logic. This self-service approach maintains simulation speed while ensuring reliable tracking of indeterminate values through the circuit.
Data Source
AI summary
To provide a logic verification apparatus capable of preventing, when an indeterminate value is generated in logic verification, the indeterminate value from being unintentionally erased. A simulation part performs a simulation based on a description of the logic function described in a hardware description language. A second symbol replacing part replaces an indeterminate value generated in the simulation by the simulation part with a symbol. The simulation part generates a symbol expression and propagates it to an element at a later stage when the symbol replaced by the second symbol replacing part reaches an element being processed. Therefore, unintentional erasing of the indeterminate value generated during the simulation can be prevented.