Multicore Memory Logical Address Distribution via Modulo Shuffling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current workload distribution schemes in multicore memory systems face challenges with load balancing and performance drops, particularly in scenarios with random workloads, leading to uneven distribution and potential premature device failure.
Innovation Solution
A scheme that distributes logical addresses to multiple cores using a combination of modulo and shuffling operations, ensuring balanced workload distribution across cores through the calculation of subsets and indices, thereby preventing performance drops and extending device lifespan.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If logical addresses are distributed to multiple cores using conventional schemes, then workload distribution is achieved, but load balancing deteriorates and performance drops in random workload scenarios
Solution Approach 1:
The patent segments the logical address space into multiple subsets, where each subset is assigned to a specific core. This segmentation is achieved by dividing the address range [LBA_start, LBA_end] into N subsets using modulo operations, where N is the number of cores. Each core processes only its assigned subset, ensuring balanced workload distribution and preventing any single core from becoming a bottleneck, thereby resolving the load balancing issue while maintaining productivity.
Solution Approach 2:
The patent implements dynamic workload distribution by using shuffling operations on the segmented address subsets. The shuffling dynamically reassigns address ranges to cores based on current system state, allowing the system to adapt to varying workload patterns. This dynamic approach prevents performance degradation in random workload scenarios by continuously optimizing the distribution pattern rather than using static assignment.
2Speed
If workload is concentrated on fewer cores, then processing speed may increase for specific tasks, but device lifespan deteriorates due to uneven distribution and premature failure
Solution Approach 1:
The patent incorporates feedback mechanisms through the shuffling operation that monitors and adjusts address subset assignments based on core workload states. When certain cores become overloaded or underutilized, the shuffling redistributes address ranges to balance the load. This feedback-driven dynamic redistribution ensures that no single core is over-stressed, preventing premature failure and extending device lifespan while maintaining overall processing speed through efficient parallel utilization of all cores.
3Device complexity
If simple address distribution methods are used, then implementation complexity is reduced, but distribution evenness deteriorates leading to performance issues
Solution Approach 1:
The patent replaces complex mechanical or manual address distribution mechanisms with mathematical operations—specifically modulo and shuffling operations. These mathematical methods provide a systematic, automated approach to achieving even distribution without requiring complex control logic. The modulo operation efficiently segments addresses, while shuffling introduces the necessary randomness to ensure evenness, together providing a computationally simple yet effective solution that maintains both low implementation complexity and high distribution evenness.
Data Source
AI summary
A workload distribution scheme is provided for a multicore memory system. The memory system includes a memory device including blocks and a controller including cores. The controller receives multiple logical addresses from a host, determines a range of logical addresses among the multiple logical addresses to be allocated for the cores, and distributes multiple subsets of the logical addresses in the range to the cores, based on an operation of modulo and shuffling on the multiple logical addresses.