Prefetching Logical Address Hints to Reduce Read I/O Latency

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Solution Overview

Problem

Existing data storage systems experience increased read I/O latency and performance penalties due to cache misses and the traversal of metadata (MD) pages, especially when read operations are directed to logical addresses not owned by the receiving node.

Innovation Solution

The system partitions ownership of the logical address space among multiple processing nodes, allowing a non-owner node to issue a request to the owner node for resolution processing. The owner node performs address resolution using MD pages and returns an address hint, which the non-owner node uses to access the requested data.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a non-owner node receives a read I/O request for a logical address it does not own, then the system maintains distributed access control, but the read I/O latency increases due to additional resolution processing

Engineering Contradiction:
Improvedistributed access controlVSAvoidread I/O latency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The owner node proactively sends address hints for logical addresses to non-owner nodes before actual read I/O requests arrive. This preliminary action allows non-owner nodes to have cached address information ready, eliminating the need for resolution processing when read requests are received, thus reducing read I/O latency while maintaining distributed access control

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces an address hint mechanism that acts as an intermediary between the owner node and non-owner nodes. Instead of directly resolving logical addresses during read operations, the system uses pre-computed address hints as intermediaries that provide direct paths to data, reducing the resolution overhead and latency

Inventive Principle:
Principle #24Intermediary (Mediator)

2Measurement precision

If the owner node performs full address resolution processing for each read request, then address accuracy is maintained, but the processing overhead increases

Engineering Contradiction:
Improveaddress resolution accuracyVSAvoidprocessing overhead
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The owner node performs address resolution processing in advance and stores the results as address hints. This preliminary resolution maintains address accuracy while eliminating the need for repeated full resolution processing during actual read operations, thus reducing processing overhead

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

Instead of performing full address resolution processing for each read request, the system creates simplified copies (address hints) of the resolution information. These copies contain the essential mapping information needed to quickly locate data without requiring complete resolution processing, reducing overhead while maintaining accuracy

Inventive Principle:
Principle #26Copying

3Productivity

If address hints are cached in non-owner nodes, then subsequent read operations are faster, but cache consistency management becomes more complex

Engineering Contradiction:
Improveread operation speedVSAvoidcache consistency management
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The system implements a feedback mechanism where the owner node tracks which non-owner nodes have received address hints for which logical addresses. When data is updated or moved, the owner node can send invalidation notifications or updated hints to the appropriate non-owner nodes, ensuring cache consistency while allowing fast reads

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS12298908B2Prefetching by logical address owner in response to peer node mapping request
Publication Date: 2025.05.13 DELL PROD LP
  • US12298908B2 patent drawing
  • US12298908B2 patent drawing
  • US12298908B2 patent drawing

AI summary

In one embodiment, processing can include: receiving, at a first node, a read I/O to read content C1 of logical address LA, wherein the first node does not own LA; and responsive to determining a hash table of the first node does not include a matching entry for LA, performing processing including: sending a request from the first node to a second node that owns LA; sending, to the first node, a response including an address hint for LA and additional address hints for logical addresses, wherein LA and the additional address hints are included in a logical address subrange associated with a single metadata page used in mapping LA and the logical addresses to physical storage locations that store content of LA and the logical addresses; the first node adding entries to the hash table for the additional address hints; and obtaining C1 using the address hint for LA.