Logical Address Key for PCRAM Error Detection
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Solution Overview
Problem
New types of non-volatile, random-access memories like PCRAM face challenges in detecting mapping-related errors due to dynamic logical to physical address mappings, which existing technologies are unable to effectively address.
Innovation Solution
A process involving a storage controller that generates a logical address key based on both logical addresses and metadata, systematically encodes this key with write data, and performs error correction decoding during read operations to detect and correct errors, allowing for the detection of erroneous mappings between logical and physical addresses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If dynamic logical to physical address mapping is used in PCRAM systems, then memory flexibility and adaptability are improved, but the ability to detect mapping-related errors deteriorates
Solution Approach 1:
The patent applies preliminary action by generating a logical address key from the logical address before the write operation, and storing this key alongside the data. During read operations, the logical address key is regenerated and used to verify data integrity, enabling error detection before errors propagate
Solution Approach 2:
The patent introduces a logical address key as an intermediary element that mediates between the logical address and the stored data. This key serves as a verification mechanism that enables error detection without interfering with the dynamic address mapping functionality
2Quantity of substance
If limited bits are allocated for error correction in small block sizes, then storage capacity is improved, but error correction capability deteriorates
Solution Approach 1:
The patent segments the error correction function into two parts: (1) a logical address key generated from the logical address that identifies the expected data, and (2) a hash of the stored data. By comparing these two segments, the system achieves effective error detection without requiring extensive error correction bits
Solution Approach 2:
The patent changes the parameter approach from traditional error correction codes that require multiple bits to a hash-based verification method. This parameter change enables effective error detection with minimal additional bits, preserving storage capacity while maintaining reliability
Data Source
AI summary
A logical address key is generated based at least in part on a logical address. Encoded data is generated by systematically error correction encoding the logical address key and write data. One or more physical addresses are determined that correspond to the logical address where the physical addresses that correspond to the logical address are dynamic. At the physical addresses, the encoded data is stored with the logical address key removed.