Multi-Dimensional Logical Address Section Table for Storage Mapping
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Solution Overview
Problem
As data storage devices grow in size, the time required to find a physical address increases due to larger mapping tables, degrading access efficiency.
Innovation Solution
A multi-dimensional logical address section table is introduced, allowing the memory controller to determine whether to search the physical to logical address mapping table based on section bit statuses, reducing unnecessary searches and optimizing access performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the size of memory blocks and the number of pages per memory block increase to expand storage capacity, then the storage capacity is improved, but the size of the mapping tables increases which causes the time required to find physical addresses to increase and access efficiency to degrade
Solution Approach 1:
The patent divides the logical address space into multiple logical address sections, each tracked by a separate section bit in the logical address section table. This segmentation allows the memory controller to check multiple section bits simultaneously to determine whether a physical address search is necessary, rather than searching the entire mapping table for every access request.
Solution Approach 2:
The patent introduces a multi-dimensional logical address section table with section bits in multiple dimensions (e.g., first dimension section bits and second dimension section bits). This multi-dimensional structure allows for more efficient addressing and filtering of logical address sections, reducing the search space in the physical to logical address mapping table by evaluating address validity across multiple dimensional criteria simultaneously.
2Quantity of substance
If the size of mapping tables increases to support larger memory blocks and more pages, then the storage capacity is improved, but the complexity of the address mapping system increases and access performance degrades
Solution Approach 1:
The logical address space is segmented into multiple logical address sections, with each section represented by a specific section bit in the logical address section table. This segmentation simplifies the address mapping process by allowing the memory controller to independently evaluate each section bit to determine search necessity, rather than managing a single large mapping table with uniform complexity.
Solution Approach 2:
The patent employs a multi-dimensional logical address section table structure with section bits organized in multiple dimensions. This multi-dimensional organization provides a systematic framework for managing large address spaces, breaking down the complexity into manageable dimensional components that can be evaluated independently and combined for final address validation.
Data Source
AI summary
A data storage device includes a memory device and a memory controller. The memory controller is coupled to the memory device and configured to access the memory device and establish a physical to logical address mapping table and a logical address section table. The logical address section table records statuses of a plurality of logical address sections. Each status is utilized to indicate whether the physical to logical address mapping table records any logical address that belongs to the corresponding logical address section. The logical address section table includes a plurality of section bits in a plurality of dimensions. When the memory controller receives a write command to write data of a first predetermined logical address, the memory controller determines the section bit of each dimension corresponding to the first predetermined logical address, and accordingly sets a corresponding digital value for each section bit.