Logical APIC ID Creation for Efficient Interrupt Routing
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Solution Overview
Problem
Current interrupt routing methods, particularly in multi-core processor systems, lead to performance and power inefficiencies due to broadcasting interrupts to all processors, which results in unnecessary traffic and power consumption, as each processor checks for interrupts even when in low power states.
Innovation Solution
Creating logical APIC IDs that group processors within the same package, allowing interrupts to be directed efficiently, reducing interconnect traffic and power consumption by only targeting the relevant processor package, and using processor selection logic to choose an available processor to respond to interrupts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If interrupts are broadcast to all processors, then all processors can receive interrupt information, but power consumption increases and processors cannot stay in deep low power states
Solution Approach 1:
The patent segments the processor system into logical groups (clusters or groups of processors) and divides interrupt routing into two stages: first routing to the appropriate cluster/package level, then distributing to specific processors within that cluster. This segmentation allows processors in other clusters to remain in low power states without receiving interrupt broadcasts, thereby reducing power consumption while maintaining reliable interrupt delivery to the target processor.
2Reliability
If interrupts are broadcast to all processors, then interrupt information is delivered to all processors, but interconnect traffic increases unnecessarily
Solution Approach 1:
The patent implements hierarchical interrupt routing that segments the broadcast domain into processor packages or clusters. Instead of broadcasting to all processors system-wide, interrupts are first routed to the specific package or cluster containing the target processor, then distributed locally. This reduces interconnect traffic significantly while maintaining reliable interrupt delivery to the intended processor.
Solution Approach 2:
The patent introduces package-level interrupt controllers or cluster managers as intermediary components that receive interrupts from the system-wide APIC and distribute them to appropriate processors within the package. These intermediaries act as filters that prevent unnecessary interrupt traffic from reaching processors in other packages, reducing overall interconnect traffic while ensuring reliable delivery to target processors.
3Adaptability or versatility
If logical APIC IDs are assigned without regard to physical topology, then operating system flexibility is improved, but interrupt routing complexity increases
Solution Approach 1:
The patent segments the APIC ID space into two components: a package/cluster identifier and a local processor identifier within that package. This segmentation allows the OS to assign logical IDs with flexibility for grouping processors however needed, while the hardware automatically handles the routing complexity by using the package ID to direct interrupts to the correct physical location. This resolves the contradiction by separating the logical ID assignment flexibility from the physical routing complexity.
Solution Approach 2:
The patent introduces redirection tables or mapping structures as intermediaries between the logical APIC ID space and the physical routing infrastructure. These tables store the correspondence between logical IDs and physical package/processor locations, allowing the OS to assign IDs flexibly while the intermediary structure handles the complex routing translation. This mediator absorbs the complexity of mapping flexible logical IDs to fixed physical locations.
Data Source
AI summary
In some embodiments, an apparatus includes logical interrupt identification number creation logic to receive physical processor identification numbers and create logical processor identification numbers through using the physical processor identification numbers. Each of the logical processor identification numbers corresponds to one of the physical processor identification numbers, and the logical processor identification numbers each include a processor cluster identification number and an intra-cluster identification number. The processor cluster identification numbers are each formed to include a group of bits from the corresponding physical processor identification number shifted in position, and the intra-cluster identification numbers are each formed in response to values of others of the bits of the corresponding physical processor identification number. Other embodiments are described.