Logical Cache Management for CPU Processing Time Reduction
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Solution Overview
Problem
Conventional cache management systems face inefficiencies in write operations due to the need for logical-to-physical address mappings, leading to inefficient data organization and increased CPU processing time, especially when dealing with geographically dispersed cache regions.
Innovation Solution
Implementing a cache management system that organizes cache memory based on logical addresses, using a write buffer to temporarily store data for relocation to general memory storage, where data is logically organized to increase physical locality, and employing a DMA controller for efficient data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If cache memory is organized based on physical addresses, then data can be stored in geographically dispersed regions, but CPU processing time increases due to logical-to-physical address mappings and scatter-gather DMA controllers are required
Solution Approach 1:
The patent inverts the conventional approach by organizing cache memory based on logical addresses instead of physical addresses. This allows data to be accessed directly using logical addresses without requiring address translation, thereby reducing CPU processing time while maintaining proper data organization.
Solution Approach 2:
The patent extracts the address translation function from the CPU processing path by implementing a separate logical-to-physical address mapping mechanism that operates independently. This allows the CPU to work directly with logical addresses in the cache while physical address mappings are handled separately, reducing CPU overhead.
2Productivity
If write operations use traditional cache management, then data can be stored in cache, but inefficient data writing occurs due to lack of physical locality
Solution Approach 1:
The patent implements a write buffer that temporarily stores write operations and organizes them before executing the actual write to storage. This preliminary organization ensures that data is written in an optimized sequence that improves physical locality, thereby increasing write operation efficiency and reducing energy loss.
Solution Approach 2:
The patent introduces a write buffer as an intermediary between the cache and general memory storage. This buffer allows data to be temporarily held and reorganized according to physical locality requirements before being written to storage, resolving the contradiction between cache organization and write efficiency.
3Ease of operation
If cache memory is organized by physical addresses, then data storage is straightforward, but requests for data from the same file must be serviced from geographically dispersed regions of the cache
Solution Approach 1:
The patent inverts the conventional cache organization by using logical addresses as the basis for cache line placement instead of physical addresses. This ensures that data requests for the same file are serviced from geographically contiguous regions of the cache, improving data access speed while maintaining ease of operation through logical address sequencing.
Data Source
AI summary
A computer system is set forth that includes a processor, general memory storage, and cache memory for temporarily storing selected data requested from the general memory storage. The computer system also may include file system software that is executed by the processor. The file system software may be used to manage the file data and the structure of the file system for files stored on the general memory storage. Management of the cache memory is placed under the control of cache management software. The cache management software is executed by the processor to manage the contents of the cache memory pursuant to cache hit and cache miss criterion. Sections of the cache memory are organized by the cache management software based on logical addresses of file data requested from the general memory storage.