Logical Clock System for Distributed Event Ordering

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Solution Overview

Problem

Distributed systems lack a global clock that provides accurate time to all networked machines, leading to challenges in event ordering, conflict resolution, and staleness detection due to independent component failures and clock skew uncertainties.

Innovation Solution

A logical clock system with bounded uncertainty is introduced, where a global time source node sets a global timestamp using message exchange between nodes, enabling strong consistency and efficient event ordering, conflict resolution, and staleness detection across the distributed system.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If a global clock is implemented in a distributed system, then time synchronization and event ordering accuracy are improved, but system complexity and failure points increase

Engineering Contradiction:
Improvetime synchronization accuracyVSAvoidsystem complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent introduces logical clocks as intermediary components at each node that mediate between local hardware clocks and the need for global event ordering. Each node maintains a logical clock that increments with local events and synchronizes with neighbors through message exchange, avoiding the need for a centralized global clock while achieving time synchronization accuracy.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent divides the global time synchronization problem into local segments by implementing logical clocks at individual nodes. Each node independently manages its own logical clock and synchronizes with adjacent nodes through bounded uncertainty intervals, breaking down the complex global synchronization task into manageable local operations.

Inventive Principle:
Principle #1Segmentation

2Measurement precision

If logical clock synchronization is performed frequently to reduce uncertainty, then time accuracy is improved, but network bandwidth consumption and processor loads increase

Engineering Contradiction:
Improveclock synchronization accuracyVSAvoidnetwork bandwidth consumption
Core Design Contradiction:
Measurement precisionVSLoss of energy

Solution Approach 1:

The patent implements periodic logical clock synchronization where nodes exchange timestamp messages at regular intervals rather than continuously. This periodic action maintains time synchronization accuracy within bounded uncertainty while significantly reducing network bandwidth consumption compared to continuous synchronization.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The logical clock system operates autonomously at each node, with nodes independently maintaining their own clock state and only exchanging minimal timestamp information when needed. This self-service approach reduces processor loads and network traffic compared to centralized clock management.

Inventive Principle:
Principle #25Self-service

3Stability of the object's composition

If bounded uncertainty intervals are maintained through message exchange, then event ordering consistency is improved, but message overhead and system latency increase

Engineering Contradiction:
Improveevent ordering consistencyVSAvoidsystem latency
Core Design Contradiction:
Stability of the object's compositionVSLoss of time

Solution Approach 1:

The patent pre-establishes bounded uncertainty intervals between nodes through initial message exchange, allowing nodes to determine event ordering consistency without continuous communication. This preliminary action creates a stable foundation for event ordering that reduces subsequent message overhead and system latency.

Inventive Principle:
Principle #10Preliminary action

4Reliability

If the system tolerates component failures, then availability is improved, but clock skew uncertainty increases

Engineering Contradiction:
Improvesystem availabilityVSAvoidclock synchronization accuracy
Core Design Contradiction:
ReliabilityVSMeasurement precision

Solution Approach 1:

The patent incorporates bounded uncertainty intervals as a cushion that accommodates clock skew variations caused by component failures. By pre-establishing these uncertainty bounds, the system can tolerate failures and node departures while maintaining event ordering consistency, improving availability without completely sacrificing synchronization accuracy.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

Data Source

PatentUS10609137B2Global logical timestamp
Publication Date: 2020.03.31 MICROSOFT TECHNOLOGY LICENSING LLC
  • US10609137B2 patent drawing
  • US10609137B2 patent drawing
  • US10609137B2 patent drawing

AI summary

Examples of the disclosure provide for providing a global timestamp in a distributed system. A plurality of nodes are connected via a network. A logical clock is implemented on a node of the plurality of nodes. The logical clock sets a global time for the network, such that another node of the plurality of nodes labels a local event with a global timestamp interval based on the global time provided by the logical clock.