Logical Clock Value for Causal Consistency in Replicated State Machines

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Solution Overview

Problem

Existing state machine replication systems face challenges in ensuring causal consistency and efficiency during distributed reads, particularly when performing state updates across multiple sets of replicated state machines, leading to scalability issues and potential data inconsistencies.

Innovation Solution

Implementing a system where each state machine maintains both a wall clock value and a logical clock value, with the primary state machine advancing its clock value based on wall clock time and propagating it to other state machines, ensuring that secondary state machines can service read requests efficiently and consistently by comparing clock values.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If state machine replication is used to ensure fault tolerance, then system reliability is improved, but device complexity increases due to multiple replicated state machines and coordination overhead

Engineering Contradiction:
Improvefault toleranceVSAvoidsystem complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent introduces a logical clock value as an intermediary mechanism that mediates between multiple replicated state machines. This logical clock serves as a common reference that simplifies the coordination complexity by providing a straightforward causality ordering mechanism, replacing more complex vector clock approaches while maintaining fault tolerance through the replicated state machine architecture

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If distributed reads are implemented by having each state machine maintain its own sequence number, then read scalability is improved, but measurement precision deteriorates due to difficulty in determining causal consistency

Engineering Contradiction:
Improveread scalabilityVSAvoidcausal consistency determination
Core Design Contradiction:
ProductivityVSMeasurement precision

Solution Approach 1:

The patent changes the parameter used for causal consistency determination from individual state machine sequence numbers to a unified logical clock value. This parameter change enables secondary state machines to accurately determine whether they can service read requests by simply comparing the logical clock value in the read request with their current logical clock value, improving both precision and scalability

Inventive Principle:
Principle #35Parameter changes

3Ease of operation

If secondary state machines service read requests using their own sequence numbers, then ease of operation is improved, but reliability worsens due to potential data inconsistencies when state machines are out of date

Engineering Contradiction:
Improveread request handlingVSAvoiddata consistency
Core Design Contradiction:
Ease of operationVSReliability

Solution Approach 1:

The patent implements a feedback mechanism where secondary state machines continuously update their logical clock value based on the latest state update messages from the primary state machine. This feedback ensures that when secondary state machines service read requests, they use their current logical clock value to verify causal consistency, guaranteeing that they return up-to-date data while maintaining ease of operation

Inventive Principle:
Principle #23Feedback

4Reliability

If vector clocks are used to track causality across multiple replicated state machine sets, then reliability is improved, but device complexity increases due to overhead of maintaining and comparing vector clock values

Engineering Contradiction:
Improvecausal consistencyVSAvoidclock management overhead
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts the essential causality tracking function from the complex vector clock mechanism and implements it using a simpler logical clock value. By taking out only the necessary element (a single scalar clock value that monotonically increases with each state update) while discarding the complex vector structure, the patent maintains causal consistency reliability while significantly reducing the overhead of maintaining and comparing clock values across multiple replicated state machine sets

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS10564665B2Performing scalable, causally consistent reads using a logical wall clock
Publication Date: 2020.02.18 MICROSOFT TECHNOLOGY LICENSING LLC
  • US10564665B2 patent drawing
  • US10564665B2 patent drawing
  • US10564665B2 patent drawing

AI summary

A first set of replicated state machines includes a first state machine that compares a clock value included in a state update message incremented by a first amount, a clock value for the first state machine incremented by a second amount, and a current local wall clock value for the first state machine to determine a maximum value and assigns the maximum value as the clock value for the first state machine. Additionally, in response to a passage of an amount of time, the first state machine advances the clock value for the first state machine to its current local wall clock value and propagates this clock value to the other state machines in the first set of replicated state machines. The advancement of the clock value for all state machines even in the absence of state updates improves their ability to respond to distributed read requests.