Logical Unit Erase Using Key Change and Scrambled FTL Metadata

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Solution Overview

Problem

Existing memory devices face challenges in quickly and securely erasing data while meeting power and resource restrictions, particularly in mobile devices, where conventional erase operations are lengthy and vulnerable to data recovery.

Innovation Solution

Implementing a logical erase operation by changing the encryption key used for encrypting critical metadata fields and logical-to-physical address maps, ensuring data is rendered unrecoverable by using scrambled data and encrypted scrambler seeds, which are updated during the erase process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of time

If conventional erase operations are used, then data is erased from memory devices, but the erase operations are lengthy and consume excessive time

Engineering Contradiction:
Improveerase operation timeVSAvoiddata erasure speed
Core Design Contradiction:
Loss of timeVSProductivity

Solution Approach 1:

The patent extracts the essential function of data erasure from physical memory cell modification and separates it into a logical operation. Instead of erasing data by physically clearing memory cells, the system extracts only the critical metadata fields and address maps that contain the actual data references, and selectively encrypts/scrambles only these extracted portions. This allows the majority of memory cells to remain untouched and quickly marked as erased, dramatically reducing erase operation time while maintaining security.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent changes the parameter of data representation by transforming readable data into encrypted or scrambled form through cryptographic transformations. By applying encryption keys or scrambling sequences to critical metadata and address maps, the data becomes mathematically unrecoverable without the corresponding decryption key. This parameter change from plaintext to ciphertext form achieves secure erasure without requiring physical destruction of memory cells, enabling fast logical erasure operations.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If physical erase operations are performed to ensure data security, then data recovery is prevented, but power consumption and resource usage increase

Engineering Contradiction:
Improvedata securityVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent extracts only the critical portions of data (metadata fields and address maps) that actually contain references to stored data, and applies encryption or scrambling exclusively to these extracted elements. The bulk of memory cells containing actual user data are not physically modified or erased. This selective extraction and encryption approach ensures data security by making retrieved data unreadable while consuming minimal power compared to physical erase operations that would require modifying every memory cell.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent replaces the mechanical/physical erase operation (which involves applying high voltages to physically alter memory cell states) with a cryptographic software-based operation. Instead of using physical mechanisms to clear memory cells, the system uses mathematical encryption algorithms and key management to achieve the same security outcome. This substitution of cryptographic operations for physical erase mechanisms dramatically reduces power consumption and resource usage while maintaining or enhancing data security.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

3Productivity

If encryption keys are changed to erase data, then erase speed is improved, but circuit area and complexity increase

Engineering Contradiction:
Improveerase operation speedVSAvoidcircuit area
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent extracts and encrypts only the critical metadata fields and address maps rather than encrypting entire memory blocks or requiring complex physical erase circuits. By focusing encryption resources on these small, critical data structures, the system achieves fast logical erasure without requiring large encryption hardware or complex circuit modifications across the entire memory device. The minimal circuit area required is sufficient to handle encryption of only the extracted metadata portions.

Inventive Principle:
Principle #2Taking out (Extraction)

4Ease of operation

If conventional erase methods are used, then data can be erased, but the data remains vulnerable to recovery attacks

Engineering Contradiction:
Improvedata erasure simplicityVSAvoiddata recovery vulnerability
Core Design Contradiction:
Ease of operationVSObject-affected harmful factors

Solution Approach 1:

The patent extracts the critical metadata fields and address maps that contain the actual data references, and applies encryption or scrambling exclusively to these extracted elements. This selective extraction ensures that even if an attacker gains physical access to memory cells, they cannot recover meaningful data because the critical addressing and metadata information is encrypted. The simplicity of logical erase operations is maintained while security is enhanced through this targeted extraction and encryption approach.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent introduces cryptographic keys and scrambling sequences as intermediary elements between the stored data and its readable form. These intermediaries act as mathematical locks that must be broken to access the actual data. Even though data physically remains in memory cells, the intermediary encryption layer prevents unauthorized recovery, making the data effectively erased from a security perspective while maintaining operational simplicity.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS12547552B2Low cost and low latency logical unit erase
Publication Date: 2026.02.10 LODESTAR LICENSING GROUP LLC
  • US12547552B2 patent drawing
  • US12547552B2 patent drawing
  • US12547552B2 patent drawing

AI summary

A memory control unit of a memory device includes at least one hardware processor; and memory storing instructions that cause the at least one hardware processor to perform operations comprising: generating a scrambler seed and a logical block address (LBA) for a block of write data received by the memory control unit from a host device; generating a flash translation layer (FTL) to map the LBA to a physical address (PA); scrambling the block of data using the scrambler seed; encrypting the scrambler seed, the LBA, and the PA in the FTL using an encryption key; initiating writing a scrambled block of data and encrypted LBA and scrambler seed to a memory array; and decrypting the FTL using an incorrect encryption key in response to an erase command received by the memory control unit from the host device.