Logical Extended Map for Multi-Threaded Core Scheduling
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Solution Overview
Problem
Multithreaded processor cores experience interference among threads, which affects performance and hinders the benefits of concurrent execution, necessitating effective task assignment to mitigate interference.
Innovation Solution
A method and system that provide a core-centric view of hardware threads and associated caches through a logical extended map, allowing the operating system to manage and schedule tasks based on thread availability and priority, utilizing user space, kernel space, cache, memory, and non-memory resources across multiple threads.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple hardware threads execute concurrently on a single processor core, then total throughput per core is improved, but thread interference increases and performance is degraded
Solution Approach 1:
The patent segments the processor core resources by creating separate logical views for different thread types (user space and kernel space threads). The core is divided into multiple hardware threads, each with its own logical processor view, allowing independent management and scheduling. This segmentation reduces interference by isolating thread contexts while maintaining concurrent execution capability.
Solution Approach 2:
The patent introduces an intermediary layer (the logical extended map and scheduling manager) between the operating system and the physical processor core. This intermediary manages thread allocation, monitors core state, and makes scheduling decisions to minimize thread interference while maximizing throughput. The scheduling manager acts as a mediator that balances the competing demands of multiple threads.
2Measurement precision
If a logical extended map is created to track thread usage of caches and memory, then task scheduling accuracy is improved, but system complexity increases
Solution Approach 1:
The logical extended map serves multiple functions simultaneously: it tracks cache usage, monitors memory access patterns, records thread availability, and provides scheduling information. This multi-functionality reduces the need for separate tracking mechanisms, thereby managing complexity while providing comprehensive measurement precision for thread usage across all resource types.
Solution Approach 2:
The patent adds a logical dimension to the physical processor map by creating virtual representations of core threads and their resource usage. This logical extended map exists in a different dimension from the physical hardware, allowing comprehensive tracking of thread states, cache hits/misses, and memory usage without adding physical complexity to the processor architecture itself.
Data Source
AI summary
A computer system is provided with a processing chip having one or more processor cores, with the processing chip in communication with an operating system having kernel space and user space. Each processor core has multiple core threads to share resources of the core, with each thread managed by the operating system to function as an independent logical processor within the core. A logical extended map of the processor core is created and supported, with the map including each of the core threads indicating usage of the operating system, including user space and kernel space, and cache, memory, and non-memory. An operating system scheduling manager is provided to schedule a routine on the processor core by allocating the routine to different core threads based upon thread availability as demonstrated in the map, and thread priority.