Logical-to-Hardware Slot Mapping for GPU Shader Scheduling
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Solution Overview
Problem
As graphics processing units (GPUs) become more powerful with increasing numbers of shader cores, existing work distribution and scheduling techniques in graphics processors significantly affect performance and power consumption, necessitating improved methods for distributing graphics work across replicated processing elements.
Innovation Solution
The implementation of logical slot to distributed hardware slot mapping techniques, including primary control circuitry that assigns work from logical slots to distributed hardware slots using various distribution modes, software overrides, and affinity-based scheduling to optimize performance and reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the number of shader cores is increased to enhance compute capabilities, then processing power is improved, but work distribution and scheduling complexity increases
Solution Approach 1:
The patent segments the work distribution system into multiple independent data masters (vertex data master, pixel data master, compute data master), each responsible for specific types of work. This segmentation allows each data master to independently manage and distribute work to shader cores without interfering with others, reducing the overall scheduling complexity while maintaining high compute capabilities across numerous shader cores.
2Productivity
If more replicated shader cores are used to process graphics work, then processing throughput is improved, but power consumption increases
Solution Approach 1:
The patent implements dynamic work distribution where data masters can adaptively assign work to different shader cores based on current system state, workload characteristics, and power conditions. This dynamic approach allows the system to process graphics work efficiently across multiple shader cores while optimizing power consumption by activating only the necessary number of cores and adjusting their operational intensity based on real-time requirements.
3Device complexity
If work distribution techniques are simplified for ease of implementation, then device complexity is reduced, but performance optimization capability deteriorates
Solution Approach 1:
The patent creates universal data master structures that can handle multiple types of graphics work (vertex processing, pixel processing, compute tasks) through a common interface and distribution mechanism. This multi-functional design simplifies the overall system architecture by eliminating the need for separate specialized distribution logic for each work type, while still achieving performance optimization through adaptive work assignment across shader cores.
Data Source
Figure 1A~1B
Figure 2
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AI summary
Disclosed techniques relate to work distribution in graphics processors. In some embodiments, an apparatus includes circuitry that implements a plurality of logical slots and a set of graphics processor sub-units that each implement multiple distributed hardware slots. The circuitry may determine different distribution rules for first and second sets of graphics work and map logical slots to distributed hardware slots based on the distribution rules. In various embodiments, disclosed techniques may advantageously distribute work efficiently across distributed shader processors for graphics kicks of various sizes.