Logical Interleaver Layout for Multi-Cell Upset Protection
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Solution Overview
Problem
Conventional memory devices face challenges in protecting against multi-cell upsets (MCU) under low-voltage operations, as physical interleaving can cause imbalances in memory aspect ratios, affecting power, performance, and area, and existing error correction codes may not effectively correct 2-bit errors.
Innovation Solution
Implementing logical interleaving in addition to physical interleaving, using a second interleaving circuit to interleave data bits from multiple data words, generating a second error correction code and storing modified data words, which complements physical interleaving to enhance error protection during low-voltage and retention modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If physical interleaving is used to protect against multi-cell upsets, then error protection capability is improved, but memory aspect ratio becomes imbalanced affecting power, performance, and area
Solution Approach 1:
The patent divides the interleaving function into two separate segments: physical interleaving (handling bit-level distribution across memory cells) and logical interleaving (handling word-level distribution across memory banks). This segmentation allows each component to be optimized independently, preventing the aspect ratio imbalance that would result from using physical interleaving alone for all error protection needs.
Solution Approach 2:
The patent introduces logical interleaving as an additional dimension of error protection that operates at the word level rather than the bit level. This adds a new dimension to the error protection capability without requiring the physical spatial distribution that causes aspect ratio imbalance, thereby resolving the contradiction between reliability improvement and device complexity.
2Use of energy by moving object
If lower supply voltage is used for runtime operations, then power consumption is reduced, but multi-cell upset probability and number of affected bits increase
Solution Approach 1:
The patent applies logical interleaving as a preliminary action before data storage, which distributes data bits across different memory banks in a way that prevents multi-cell upsets from affecting multiple bits within the same codeable data unit. This preliminary distribution maintains error protection capability even when operating at lower supply voltages where MCU probability increases.
Solution Approach 2:
The patent implements logical interleaving as a protective measure that cushions against the increased multi-cell upset risk associated with low-voltage operation. By pre-distributing data bits across independent memory banks, the system creates a buffer that prevents voltage-related MCUs from causing catastrophic failures, thereby maintaining reliability during low-power operations.
3Reliability
If large physical interleaving size is used to handle multi-cell upsets, then error correction capability is improved, but memory footprint aspect ratio becomes imbalanced
Solution Approach 1:
The patent segments the error protection function into physical interleaving for bit-level distribution and logical interleaving for word-level distribution. This allows the system to achieve comprehensive MCU handling capability without requiring large physical interleaving sizes that would distort the memory footprint aspect ratio, as logical interleaving provides additional protection at the word level.
Solution Approach 2:
The patent introduces logical interleaving as an additional dimension of error protection that operates independently of physical memory layout. This enables the system to achieve enhanced multi-cell upset handling capability through logical word-level distribution without being constrained by physical aspect ratio considerations, effectively decoupling error protection capability from memory footprint geometry.
Data Source
AI summary
Various implementations described herein are directed to a memory device. The memory device includes a first interleaving circuit that receives data words and generates a first error correction code based on the received data words. The memory device includes a second interleaving circuit that receives the data words and generates a second error correction code based on the received data words as a complement to the first error correction code. The second interleaving circuit interleaves data bits from multiple different data words and stores modified data words based on the multiple different data words.