Logical Memory Buffers for Media Controller Parallelism
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current computing systems face inefficiencies in memory access and processing due to limited memory subunits, leading to suboptimal performance and power usage.
Innovation Solution
A media controller allocates a greater number of logical memory buffers than actual memory subunits, allowing for increased parallelism and efficient processing of memory access requests by leveraging outstanding requests and adjusting sequencing operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of memory subunits is increased to improve memory access performance, then memory access performance is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent divides the memory device into multiple memory subunits (first memory subunit, second memory subunit, etc.) that can be independently accessed. The media controller manages these segmented subunits through logical memory buffers, allowing parallel memory operations without increasing overall device complexity. Each subunit can be independently activated and precharged, enabling concurrent memory accesses.
Solution Approach 2:
The patent introduces logical memory buffers as intermediary structures between the media controller and physical memory subunits. These buffers map multiple logical memory buffers to fewer physical subunits, allowing the controller to manage memory access more efficiently. The intermediary buffer layer enables virtual memory expansion without proportionally increasing physical memory hardware complexity.
2Productivity
If the number of memory subunits is increased to improve parallelism, then memory access performance is improved, but power consumption increases
Solution Approach 1:
The patent implements preliminary actions through precharging memory subunits before they are needed for data access. The media controller precharges multiple memory subunits in advance, so when data is actually required, the subunits are already in a ready state. This reduces the power consumption during actual data access operations while maintaining high parallelism capability.
Solution Approach 2:
The patent uses periodic precharging operations where memory subunits are precharged at scheduled intervals rather than continuously. The media controller manages precharging cycles that optimize power consumption by activating subunits only when needed, rather than keeping all subunits in high-power ready states continuously.
3Productivity
If logical memory buffers are allocated greater than memory subunits to increase parallelism, then memory access performance is improved, but device complexity increases
Solution Approach 1:
The patent introduces a dimensional transformation by mapping multiple logical memory buffers to fewer physical memory subunits. Instead of having a one-to-one correspondence, the system creates a many-to-one mapping relationship. This dimensional compression allows the system to present more memory interfaces than physically exist, increasing parallelism without proportionally increasing hardware complexity.
Solution Approach 2:
The patent makes memory subunits multi-functional by allowing a single physical subunit to serve multiple logical memory buffers. The media controller dynamically assigns and reassigns physical subunits to different logical buffers based on access patterns and availability. This universality enables one physical component to perform multiple functions, reducing overall device complexity while maintaining high parallelism.
Data Source
AI summary
In some examples, a media controller includes a buffer and controller circuitry. The controller circuitry may receive, from a memory device linked to the media controller, an indication of a number of memory subunits that the memory device is divided into. The controller circuitry may also allocate, within the buffer, a number of logical memory buffers for the memory device greater than the number of memory subunits and indicate to a memory controller that a number of memory units accessible for the memory device is the number of logical memory buffers.