Logical Model Extraction for IC Defect Diagnosis
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Solution Overview
Problem
The increasing complexity of integrated circuit manufacturing processes makes fault diagnosis challenging, as existing methods often rely on insufficient fault models that fail to accurately capture the behavior of defects, particularly in nanoscale technologies, and do not adequately address the possibility of multiple or complex defect types.
Innovation Solution
A new fault diagnosis method that identifies defect sites and behavior using weaker assumptions, focusing on logical conditions of physical neighbors to derive a precise fault model, represented as macrofaults, which are validated through simulation, allowing for automated and accurate identification of defect types and locations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional fault models are used for diagnosis, then the diagnosis process is simpler, but the accuracy of defect characterization is insufficient
Solution Approach 1:
The system automatically extracts logical models of defect behavior directly from test data without requiring manual fault model specification. The diagnosis engine self-configures by analyzing test responses and synthesizing neighborhood functions that represent defect characteristics, eliminating the need for pre-defined fault models while maintaining high characterization accuracy
Solution Approach 2:
The patent replaces traditional mechanical fault modeling approaches with a data-driven logical modeling system. Instead of relying on pre-specified fault models, the system uses automated logical analysis of test data to derive defect behavior models, substituting manual model selection with automated logical synthesis from empirical evidence
2Measurement precision
If physical failure analysis is performed in detail, then diagnostic accuracy improves, but the time and complexity of the process increases significantly
Solution Approach 1:
The system performs preliminary logical analysis of test data to identify candidate defect locations and their logical models before physical failure analysis. By pre-characterizing defects at the logical level and generating targeted hypotheses about defect locations and types, the system reduces the scope and time required for subsequent physical analysis while maintaining high diagnostic accuracy
Solution Approach 2:
The diagnosis process is segmented into distinct phases: logical model extraction from test data, candidate location identification, and targeted physical analysis. This segmentation allows the system to handle complex diagnosis tasks in manageable stages, reducing overall process time while maintaining precision through systematic progression from logical to physical analysis
3Adaptability or versatility
If multiple fault models are used to cover complex defect behaviors, then diagnostic coverage improves, but the complexity of selecting and applying appropriate models increases
Solution Approach 1:
The system employs a universal logical modeling framework that can represent any defect behavior through neighborhood functions derived from test data. Instead of requiring separate fault models for different defect types, the system uses a single flexible logical modeling approach that adapts to various defect characteristics automatically, providing universal coverage without model selection complexity
Solution Approach 2:
The system changes the fundamental parameter of defect representation from fixed fault model categories to dynamically extracted logical models. By transforming defect characterization from static model selection to dynamic logical synthesis based on observed test behavior, the system achieves versatility across defect types while eliminating the complexity of choosing appropriate models
Data Source
AI summary
A method and apparatus are disclosed in which defect behavior in an integrated circuit is discovered and modeled rather than assuming defect behavior in the form of a fault. A plurality of tests are performed on an integrated circuit to produce passing and failing responses. The failing responses are examined in conjunction with circuit description data to identify fault locations. For at least certain of the fault locations, the logic-level conditions at neighboring locations which describe the behavior of a failing response are identified. Those logic level conditions are combined into a macrofault for that location. The macrofault is then validated and can be then used to identify more tests for further refining the diagnosis. Because of the rules governing abstracts, this abstract should not be used to construe the claims.