Logical Network-on-Chip Segmentation for Design Comprehensibility
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Solution Overview
Problem
Circuit designs involving network-on-chip (NoC) modules are cumbersome to comprehend and manage due to their monolithic representation, making integration of designs from different design teams difficult, especially for large NoCs with many endpoints and paths.
Innovation Solution
The method involves instantiating logical network-on-chip (LNoC) blocks in a computer system to specify connections between ingress and egress circuits, aggregating these blocks into a traffic specification, and compiling it into configuration parameters for switch circuits, allowing for a more manageable and integratable circuit design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If the NoC is presented as a monolithic component with ports for every ingress and egress point, then complete connectivity is achieved, but the design becomes difficult to comprehend and manage
Solution Approach 1:
The patent divides the monolithic NoC into multiple sub-networks, each with a limited number of ingress and egress points. This segmentation reduces the complexity of the NoC representation for each design team while maintaining complete connectivity through inter-subnetwork routing. Each sub-network can be independently understood and managed, yet collectively they provide full NoC functionality.
2Productivity
If multiple design teams work on different portions of the circuit design, then parallel development is enabled, but reconciliation of designs becomes difficult
Solution Approach 1:
The patent assigns different sub-networks to different design teams, allowing parallel development of independent portions of the overall design. Each team works on a manageable subset of the NoC without needing to understand the entire system, reducing integration complexity while enabling simultaneous development progress.
Solution Approach 2:
The patent creates a standardized interface between sub-networks that allows different design teams to use the same connection protocols and routing mechanisms. This universal interface enables seamless integration of independently developed sub-networks, maintaining multi-functionality across the entire NoC while simplifying the reconciliation process.
3Adaptability or versatility
If the NoC supports many concurrent communication paths, then communication capability is enhanced, but the number of endpoints grows large
Solution Approach 1:
The patent organizes the large number of endpoints into multiple sub-networks, each with a limited set of ingress and egress points. This segmentation maintains the ability to support many concurrent communication paths within each sub-network while reducing the apparent endpoint complexity for each design team. The inter-subnetwork routing provides additional communication paths without increasing individual sub-network complexity.
Data Source
AI summary
Disclosed approaches for creating a circuit design involving a network-on-chip (NoC) include instantiating in a memory of a computer system logic blocks and logical NoC (LNoC) blocks. Each logic block specifies a function of the circuit design and is communicatively coupled to another logic block through an LNoC block. The LNoC blocks are aggregated into a traffic specification that specifies connections between ingress circuits and egress circuits of the NoC. The traffic specification is compiled into configuration parameters for circuits of the NoC, and the logic blocks are compiled into implementation data for the target IC by the computer processor. The target IC can then be configured with the configuration parameters and implementation data.