Logical Page Address Mapping for Non-Power-of-Two NAND Layouts
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Solution Overview
Problem
Existing memory systems face challenges in maintaining consecutive logical page address spaces when the quantities of memory devices, planes, pagelines, or virtual pages are not powers of two, leading to discontinuities and inefficiencies in address space compression.
Innovation Solution
A composite bit field is used to represent memory devices, planes, and pagelines, with formulas to derive specific addresses, ensuring consecutive logical page address spaces across varying quantities, including regions with different virtual page configurations, and accounting for defective memory cells to enhance compression efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional address space methods are used with non-power-of-two quantities of memory devices, planes, or pagelines, then the system can accommodate varying memory configurations, but the logical page address space becomes discontinuous and compression efficiency deteriorates
Solution Approach 1:
The patent changes the parameter representation from traditional separate bit fields for memory device, plane, and pageline to a composite bit field that encodes consecutive logical page addresses. This parameter transformation maintains adaptability to non-power-of-two configurations while ensuring address space consecutiveness for efficient compression.
Solution Approach 2:
The patent segments the address space into logical pages that maintain consecutive ordering across different memory devices, planes, and pagelines. By dividing the address space into these segmented logical units, the system achieves both flexibility in configuration and consecutiveness in addressing.
2Adaptability or versatility
If address space compression is performed with discontinuous address spaces, then the system can handle varied memory layouts, but compression efficiency and performance deteriorate
Solution Approach 1:
The patent transforms the address representation parameters to create a consecutive logical page address space that preserves memory layout flexibility while enabling efficient compression algorithms to operate on contiguous address sequences.
Solution Approach 2:
The patent establishes continuous logical page address ordering that maintains the useful action of data sequentiality regardless of physical memory layout. This continuity enables compression operations to proceed efficiently without interruptions from discontinuous addressing.
3Reliability
If PPT flushing transactions are performed frequently to maintain address translation accuracy, then data integrity is preserved, but processing speed and response times deteriorate
Solution Approach 1:
The patent performs preliminary action by establishing a consecutive logical page address space structure that maintains address translation accuracy without requiring frequent PPT flushing. The composite bit field encoding ensures that address translations remain valid and consistent, reducing the need for frequent flushing operations.
Solution Approach 2:
The patent implements feedback mechanisms that monitor address translation validity and only trigger PPT flushing when necessary, rather than following a fixed frequent flushing schedule. This feedback-based approach maintains reliability while optimizing processing speed by avoiding unnecessary flushing operations.
Data Source
AI summary
Methods, systems, and devices for consecutive logical page address spaces are described. A controller may receive, from a host system, a command including an indication of a logical block address. The controller may determine a logical page address based on the logical block address and may transmit, to a memory device of a set of memory devices, a physical address based on the logical address. In some examples, the address space may be consecutive across virtual pages, planes, memory devices, and pagelines, where a quantity of the set of planes, a quantity of the set of memory devices, or both is not a power of two. In some examples, the address space may be consecutive over a boundary between a first portion of the address space and a second portion of the address space, each associated with memory cells having a respective quantity of virtual pages.