Logical Partition Memory Address Translation Hardware
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Solution Overview
Problem
Existing virtualization methods, such as full and paravirtualization, incur performance overhead and security risks due to hypervisor simulation of privileged operations, multiple page tables, and interrupts, which complicate real memory separation and translation between logical partitions.
Innovation Solution
A hardware-based address translation mechanism that uses a logical partition real memory map to directly translate virtual addresses into system real addresses, reducing the need for hypervisor software intervention and modifying the operating system, thereby enhancing performance and security by eliminating the need for hypervisor-controlled page table interpretation and simulation of real addressing modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If full virtualization of address translation is used, then memory isolation between partitions is achieved, but system performance deteriorates due to hypervisor simulation overhead and multiple page table lookups
Solution Approach 1:
The patent extracts the address translation function from the software hypervisor layer and implements it directly in hardware. The address translation mechanism is removed from the virtualization software and embedded into the memory management hardware, eliminating the need for software-based address translation and its associated performance overhead while maintaining memory isolation between partitions.
Solution Approach 2:
The patent introduces a hardware-based address translation mechanism as an intermediary between virtual addresses and physical memory addresses. This hardware mediator performs address translation automatically without requiring hypervisor intervention, thus maintaining memory isolation while improving performance by eliminating software overhead.
2Productivity
If paravirtualization is used to reduce overhead, then system performance improves, but security risks increase due to OS modifications and reduced isolation
Solution Approach 1:
The patent removes the need for OS modifications by extracting the address translation function from the software layer and implementing it in hardware. This allows the operating system to run unmodified while maintaining strong memory isolation, achieving both performance improvement and security without the compromises required by paravirtualization.
3Reliability
If hypervisor-controlled address translation is used, then memory security is maintained, but device compatibility deteriorates due to inability to disable virtual address translation
Solution Approach 1:
The patent implements a dynamic address translation mechanism where the hardware can adaptively switch between different translation modes. The system can dynamically disable address translation when needed for device compatibility while maintaining security through hardware-enforced memory partitioning, thus achieving both security and adaptability.
4Reliability
If multiple page tables are maintained for full virtualization, then memory isolation is ensured, but device complexity increases due to multiple translation layers
Solution Approach 1:
The patent extracts the multi-layer page table management complexity from the software hypervisor and consolidates it into a single hardware-based address translation mechanism. This eliminates the need for multiple software-maintained page tables while maintaining memory isolation, significantly reducing system complexity.
Data Source
AI summary
A mechanism is provided, in a data processing system, for accessing memory based on an effective address submitted by a process of a partition. The mechanism may translate the effective address into a virtual address using a segment look-aside buffer. The mechanism may further translate the virtual address into a partition real address using a page table. Moreover, the mechanism may translate the partition real address into a system real address using a logical partition real memory map for the partition. The system real address may then be used to access the memory.