Logical Address Partitions With Selective Power-Safe Writes

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Solution Overview

Problem

Existing memory sub-systems inefficiently handle data storage by applying power safety techniques to all data, including non-critical data, leading to reduced performance and inefficiency in systems with broad temperature ranges and high reliability requirements.

Innovation Solution

Implementing power safety configurations for logical address space partitions by allowing a memory sub-system to receive host-configured power safety information to determine whether to use power safety techniques, such as indirect XLC writes via forced SLC caching, based on the importance of data reliability for each partition.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If power safety techniques are implemented for all partitions, then data reliability is improved, but system overhead increases and performance decreases

Engineering Contradiction:
Improvedata reliabilityVSAvoidsystem performance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent applies different power safety configurations to different logical address space partitions based on their specific requirements. Critical partitions receive full power safety protection while non-critical partitions use reduced or no power safety techniques, allowing each partition to have optimized characteristics tailored to its data importance and access patterns.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The logical address space is divided into multiple partitions that can be independently configured with different power safety settings. This segmentation allows the system to apply protective measures selectively to only those partitions containing critical data, rather than uniformly protecting all data equally.

Inventive Principle:
Principle #1Segmentation

2Reliability

If indirect XLC writes via forced SLC caching are used, then data reliability is improved, but write performance and power efficiency deteriorate

Engineering Contradiction:
Improvedata reliabilityVSAvoidpower efficiency
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent enables host systems to configure power safety settings per partition, allowing direct XLC writes for non-critical data partitions while maintaining indirect writes with SLC caching only for critical partitions. This localized approach optimizes power efficiency for each partition based on its specific reliability requirements.

Inventive Principle:
Principle #3Local quality

3Loss of time

If power safety configurations are implemented, then boot time is reduced, but system complexity increases

Engineering Contradiction:
Improveboot timeVSAvoidsystem complexity
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The patent introduces dynamic power safety configurations where the host system can adjust power safety settings for different partitions based on runtime requirements. This dynamic approach allows the system to optimize boot performance by configuring non-critical partitions for faster access while maintaining protection for critical partitions.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The host system pre-configures power safety settings for each partition during system initialization or setup, allowing the memory sub-system to operate efficiently without real-time decision-making complexity. These preliminary configurations enable faster boot times while maintaining appropriate protection levels.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS12632192B2Power safety configurations for logical address space partitions
Publication Date: 2026.05.19 MICRON TECHNOLOGY INC
  • US12632192B2 patent drawing
  • US12632192B2 patent drawing
  • US12632192B2 patent drawing

AI summary

A system includes a memory device, and a processing device, operatively coupled to the memory device, to perform operations including obtaining, from a host system, a power safety configuration for a partition, wherein the power safety configuration for the partition configures the memory device to implement power safe writing for the partition by operating in a first write mode utilizing single level cell (SLC) caching, or to implement non-power safe writing for the partition by operating in a second write mode without utilizing SLC caching, and configuring the memory device to operate in the first write mode or the second write mode based on the power safety configuration.