Logical Transport Overlay on PCIe for Cache Coherency
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current bus architectures, such as PCI and PCIe, face limitations in bandwidth, real-time data transfer, quality of service, power management, and cache coherency, which are essential for next-generation I/O requirements, and replacing existing hardware is costly and error-prone.
Innovation Solution
A cache coherent bus architecture is transparently overlaid on an existing bus architecture using a logical transport network, leveraging PCIe virtual channels and Vendor Defined Messages to carry Class-of-Service attributes and optimized transaction layer packets, enabling cache coherency and low-latency data transfer without replacing physical hardware.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If PCIe bus architecture is used, then bandwidth and processor independence are improved, but cache coherency and real-time data transfer capabilities are lost
Solution Approach 1:
The patent segments the transaction layer into multiple virtual channels (VCs), where specific VCs are designated for cache coherency transactions. This segmentation allows PCIe to maintain its high-bandwidth physical transport while creating logical divisions that can enforce cache coherency protocols, thus resolving the contradiction between bandwidth and coherency support.
Solution Approach 2:
The patent introduces an intermediary transaction layer that sits between the PCIe physical transport and the endpoint devices. This intermediary layer translates and routes transactions appropriately, enabling cache coherency semantics to be imposed on top of PCIe's inherently non-coherent physical layer without replacing the underlying hardware.
2Reliability
If hardware replacement is performed to achieve cache coherency, then cache coherency is improved, but cost and implementation complexity increase
Solution Approach 1:
Instead of replacing the physical PCIe hardware, the patent creates a virtual copy of the transaction layer with cache coherency capabilities. This virtual transaction layer replicates necessary coherency functions through software-defined routing and transaction management, avoiding the need for expensive hardware replacement while achieving the desired coherency behavior.
Solution Approach 2:
The patent changes the parameters of the transaction layer by introducing new transaction types, routing rules, and virtual channel allocations that enable cache coherency. By modifying the logical parameters rather than the physical hardware, the system achieves coherency without the complexity and cost of hardware replacement.
3Reliability
If virtual channels are designated for logical transport, then data integrity and quality of service are improved, but device complexity increases
Solution Approach 1:
The patent makes the PCIe transaction layer universal by designing it to handle multiple functions through virtual channels. The same physical infrastructure supports both traditional PCIe transactions and cache coherency transactions, as well as quality-of-service differentiated traffic, thereby improving data integrity without proportionally increasing device complexity.
Data Source
AI summary
A method and a system for transparently overlaying a logical transport network over an existing physical transport network is disclosed. The system designates a virtual channel located in a first transaction layer of a network conforming to a first network protocol. The system assembles a transaction layer packet in a second logical transaction layer of a second network protocol that is also recognizable by the first transaction layer. The system transfers the transaction layer packet from the second transaction layer to the virtual channel. The system transmits the transaction layer packet over the first transaction layer using the designated virtual channel over the network.