Multi-Level Logical to Physical Mapping for Storage Capacity
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Solution Overview
Problem
Existing memory systems face challenges in efficiently managing logical to physical address mappings, particularly in reducing latency associated with access operations and maintaining storage capacity without degrading write performance or introducing drive wear out.
Innovation Solution
The implementation of a multi-level mapping system that includes a macro level for storing coarser entries when logical addresses are sequential, along with pointers to the L2P level for exceptions, allows for increased storage capabilities without degrading write performance or introducing drive wear out.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a traditional L2P mapping table is used to map logical addresses to physical addresses, then the memory system can store mapping information, but the storage capacity is limited and latency increases when the mapping table becomes large
Solution Approach 1:
The patent segments the mapping information storage into two distinct levels: a compressed mapping table for sequential logical address ranges and a full L2P mapping table for non-sequential or exception cases. This segmentation allows the system to store more mapping information (improving storage capacity) while quickly resolving common sequential cases through the compressed table (reducing access latency).
Solution Approach 2:
The patent introduces a hierarchical dimension to the mapping storage structure by organizing mapping information across two levels (compressed table and full L2P table) rather than using a single flat table. This dimensional organization enables the system to efficiently manage large volumes of mapping information while maintaining fast access performance.
2Quantity of substance
If the L2P mapping table is expanded to increase storage capacity, then more logical addresses can be mapped, but write performance degrades and drive wear out increases
Solution Approach 1:
The patent extracts the most common mapping patterns (sequential logical address ranges) into a separate compressed mapping table, removing them from the full L2P mapping table. This extraction reduces the size and update frequency of the main L2P table, thereby improving write performance and reducing drive wear while still maintaining the ability to map a large number of logical addresses through the compressed table.
3Quantity of substance
If a compressed mapping table is implemented to improve storage efficiency, then storage capacity increases, but the system complexity increases due to multiple mapping levels
Solution Approach 1:
The patent implements a dynamic mapping system where the system automatically determines which mapping table to use based on the characteristics of the logical address being accessed. For sequential addresses, the compressed table is used; for non-sequential or exception cases, the full L2P table is consulted. This dynamic approach manages system complexity by providing clear decision logic while achieving high storage efficiency.
Data Source
AI summary
Methods, systems, and devices for creating high density logical to physical mapping are described. A memory system may implement storage of mapping information to store the logical addresses and the corresponding physical addresses. A memory system may receive a command associated with data and a corresponding set of logical addresses, and in some cases the memory device may determine that the logical addresses are sequential. The memory device may generate and store a set of compressed entries in a macro level of the mapping information. When the memory system receives a command associated with an exception to the sequential logical addresses, the memory system may update an entry of the macro level to include a pointer to a set of entries in another level of the mapping information.