Secure Communication Link Using Logical Ports for Multi-Core Throughput

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Solution Overview

Problem

The existing IPSec protocol for secure networking in cloud environments is limited to approximately one gigabit per second (Gbps) of data throughput due to the lack of entropy in directing encrypted traffic to different processor cores, and this limitation is exacerbated by the constraints of available IP addresses, especially in scenarios where additional IP addresses are not readily available.

Innovation Solution

A high-performance communication link is established using multiple interconnects between computing devices, employing logical port substitution and network address translation (NAT) logic to distribute data traffic across multiple processing logic units, allowing for increased throughput without requiring additional IP addresses.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If IPSec protocol is used for secure networking, then security is improved, but data throughput is limited to approximately one gigabit per second

Engineering Contradiction:
ImprovesecurityVSAvoiddata throughput
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent segments the single IPSec connection into multiple parallel connections by introducing multiple logical ports (4501-4516) over a single physical IP address. Each logical port operates as an independent communication channel with its own processor core assignment, allowing aggregate throughput to scale beyond the 1 Gbps limit of a single connection while maintaining IPSec security encryption for all channels.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent adds a new dimension to the communication protocol by introducing logical port identifiers as an additional layer above the traditional IP address. This extra dimension enables multiple simultaneous communication streams over a single IP address, transforming the throughput limitation from a scalar constraint to a multi-dimensional solution where multiple logical channels operate in parallel.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Productivity

If multiple IP addresses are used to increase throughput, then data throughput is improved, but network operability is constrained due to IP address availability

Engineering Contradiction:
Improvedata throughputVSAvoidnetwork operability
Core Design Contradiction:
ProductivityVSAdaptability or versatility

Solution Approach 1:

The patent makes the single physical IP address universal by enabling it to serve multiple logical functions simultaneously. The single IP address can support multiple logical ports (4501-4516), each functioning as an independent communication channel. This multi-functionality allows the system to achieve the throughput benefits of multiple IP addresses while maintaining network operability with a single assigned IP address.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent introduces logical port identifiers as an intermediary layer between the IP address and the application layer. This intermediary enables multiple communication channels to be established over a single IP address by using the logical port as a mediator that distinguishes between different data streams without requiring additional IP addresses, thus resolving the conflict between throughput and network operability.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Stability of the object's composition

If IPSec encrypted traffic is directed to a specific processor core, then processing consistency is improved, but throughput is limited due to lack of distribution across multiple cores

Engineering Contradiction:
Improveprocessing consistencyVSAvoidthroughput
Core Design Contradiction:
Stability of the object's compositionVSProductivity

Solution Approach 1:

The patent applies local quality by assigning different logical ports to different processor cores based on hash computation. Instead of directing all traffic to a single core, each logical port (4501-4516) can be mapped to a specific processor core, creating localized processing paths that maintain consistency for each channel while distributing load across multiple cores. This enables both processing consistency and multi-core utilization.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent introduces dynamic processor core selection through hash computation of the logical port identifiers. The processor core assignment is not static but dynamically determined by hashing the logical port number, which allows the system to adaptively distribute traffic across available processor cores. This dynamic assignment enables throughput scaling while maintaining processing consistency within each logical channel.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS20250373541A1High-performance communication link and method of operation
Publication Date: 2025.12.04 AVIATRIX SYSTEMS INC
  • US20250373541A1 patent drawing
  • US20250373541A1 patent drawing
  • US20250373541A1 patent drawing

AI summary

Embodiments of the disclosure relate to a secure, high-performance communication link that relies on single network, multiple logical port addressing. Embodiments of an infrastructure are associated with a high-performance communication link that allows for distribution of network traffic across multiple interconnects using a single network address with different logical network port addressing. This high-performance communication link supports data traffic across different processing logic units residing within a destination computing device.