Logical Region Memory Mapping for Secure Element Virtualization

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Solution Overview

Problem

Current memory management systems for secure elements, such as smart cards, face challenges in efficiently managing limited RAM resources, leading to internal fragmentation, high resource consumption, and limitations in virtualization, which hinder fast context-switches and independent updates of multiple operating systems.

Innovation Solution

The method involves creating equally sized logical regions in a logical address space, mapping consecutive logical addresses to physical addresses, and using permission mappings to control access, allowing for efficient memory access and management with minimal hardware and power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If memory is split into big pages (4 KB or 8 KB) for virtualization, then virtualization capability is improved, but internal fragmentation increases and memory usage efficiency deteriorates

Engineering Contradiction:
Improvevirtualization capabilityVSAvoidmemory usage efficiency
Core Design Contradiction:
Adaptability or versatilityVSQuantity of substance

Solution Approach 1:

The patent segments the logical address space into equally sized logical regions that can be mapped to physical memory regions. This segmentation allows for efficient memory management in constrained environments by creating manageable units that can be independently allocated and mapped, resolving the contradiction between virtualization capability and memory efficiency.

Inventive Principle:
Principle #1Segmentation

2Adaptability or versatility

If page tables are implemented for hardware remapping, then memory virtualization is improved, but memory resource consumption increases due to large page table sizes

Engineering Contradiction:
Improvememory virtualizationVSAvoidmemory resource consumption
Core Design Contradiction:
Adaptability or versatilityVSQuantity of substance

Solution Approach 1:

The patent extracts the essential mapping functionality from traditional page tables and implements a simplified mapping mechanism using a set of equally sized logical regions. This extraction removes the overhead of large page tables while retaining the core virtualization capability, thereby reducing memory resource consumption.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent creates a simplified copy of the address mapping functionality that operates on equally sized logical regions rather than traditional page tables. This copying approach replicates the essential mapping behavior with reduced memory overhead, solving the contradiction between virtualization and resource consumption.

Inventive Principle:
Principle #26Copying

3Adaptability or versatility

If multiple independent OSes are integrated in a single device, then functionality and adaptability are improved, but system complexity and resource management difficulty increase

Engineering Contradiction:
Improvemulti-OS functionalityVSAvoidsystem complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent segments the address space into equally sized logical regions that can be independently mapped to different physical memory regions for different operating systems. This segmentation provides a structured framework for multi-OS support while maintaining manageable system complexity through consistent region sizing and mapping rules.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS11269788B2Managing memory in an electronic device
Publication Date: 2022.03.08 NXP BV
  • US11269788B2 patent drawing
  • US11269788B2 patent drawing

AI summary

There is described a method of managing memory in an electronic device, the method comprising creating a set of equally sized logical regions in a logical address space, each logical region comprising a plurality of consecutive logical addresses, and mapping a subset of consecutive logical addresses within each logical region to a set of physical addresses within a corresponding physical memory region, the subset of consecutive logical addresses comprising the first logical address within the logical region, said first logical address being mapped to a base address within the corresponding physical memory region. Furthermore, there is described a controller for managing memory in an electronic device and a method of determining a physical memory address in a physical memory region using such a controller.