Logical Time Generation for Redundant Processor Consistency

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Solution Overview

Problem

In multiple redundant processor systems, loosely synchronized processors may return different time of day responses, leading to errors when an application requests time annotation for transactions, as they execute the same instruction set but at slightly different times, causing performance degradation due to frequent requests for actual time from a common source.

Innovation Solution

Implementing time of day logic to generate a logical time that approximates the real time, ensuring all processor elements return the same logical time, which is close to the actual time within a few microseconds, thereby reducing the need for frequent synchronization and maintaining system performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If processors are loosely synchronized to execute instructions faster, then processing speed is improved, but time of day response consistency deteriorates

Engineering Contradiction:
Improveprocessing speedVSAvoidtime of day response consistency
Core Design Contradiction:
SpeedVSMeasurement precision

Solution Approach 1:

The system segments the time of day response function by having each processor element independently generate its own time response based on local execution state, rather than requiring centralized time management. This segmentation allows processors to operate independently at different speeds while maintaining consistent time annotations through the deterministic relationship between instruction execution state and time response.

Inventive Principle:
Principle #1Segmentation

2Productivity

If processors execute instructions at different times, then system performance is improved, but time annotation accuracy for transactions deteriorates

Engineering Contradiction:
Improvesystem performanceVSAvoidtime annotation accuracy
Core Design Contradiction:
ProductivityVSMeasurement precision

Solution Approach 1:

The system introduces an intermediary mechanism where the time of day response is derived from the deterministic execution state (instruction counter, program counter, register state) rather than direct clock time. This intermediary approach allows processors to execute at different speeds while producing consistent time annotations based on their equivalent execution states.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Measurement precision

If processors are tightly synchronized to maintain time consistency, then time response accuracy is improved, but processing speed deteriorates

Engineering Contradiction:
Improvetime response accuracyVSAvoidprocessing speed
Core Design Contradiction:
Measurement precisionVSSpeed

Solution Approach 1:

The system inverts the traditional approach by not synchronizing processors to maintain time consistency, but rather deriving time consistency from the processors' independent execution states. Instead of forcing processors to execute at the same time, the system allows them to execute at different speeds while maintaining time annotation consistency through their deterministic state relationships.

Inventive Principle:
Principle #13The other way round (Inversion)

4Measurement precision

If frequent actual time updates are requested from a common source, then time accuracy is improved, but system performance deteriorates

Engineering Contradiction:
Improvetime accuracyVSAvoidsystem performance
Core Design Contradiction:
Measurement precisionVSProductivity

Solution Approach 1:

Each processor element serves itself by independently generating time of day responses based on its own execution state, eliminating the need to frequently request time updates from a common source. This self-service approach maintains time accuracy while avoiding the performance degradation associated with frequent centralized time queries.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS8230252B2Time of day response
Publication Date: 2012.07.24 VALTRUS INNOVATIONS LTD
  • US8230252B2 patent drawing
  • US8230252B2 patent drawing
  • US8230252B2 patent drawing

AI summary

In an implementation of time of day response, time logic executed by each processor element of a logical processor generates a logical time in response to a time of day request. The logical time is generated to approximate the actual time such that each processor element of the logical processor returns the same logical time.