Logical Unit Operation Control Circuitry for SSD Memory
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Solution Overview
Problem
Existing memory devices face inefficiencies in controlling multiple logical units with a single command and address, leading to increased operational overhead and potential data redundancy issues, particularly in solid state drives where redundancy is crucial for reliability.
Innovation Solution
A memory device architecture that includes control circuitry capable of controlling multiple logical units with a single command and address, allowing for simultaneous programming and erasing operations across multiple units, thereby reducing operational time and overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple logical units are controlled with separate commands and addresses, then each unit can be precisely addressed, but operational overhead increases and control efficiency decreases
Solution Approach 1:
The patent merges the control of multiple logical units by enabling a single command to simultaneously address and operate on multiple logical units. The control circuitry is designed to decode a single address that can represent multiple logical units, allowing parallel control operations that reduce the number of separate commands needed while maintaining precise control over each unit.
Solution Approach 2:
The control circuitry is designed with multi-functionality to handle both traditional single-unit addressing and the new multi-unit addressing mode. The address decoding logic can universally interpret addresses to either select a single logical unit or a group of logical units based on the command type, providing flexibility without requiring separate control paths.
2Reliability
If redundancy is implemented across multiple logical units, then data reliability improves, but the complexity of managing multiple units increases
Solution Approach 1:
The patent applies merging by combining the control operations for redundant data storage across multiple logical units into a single command execution. When data is written to one logical unit, the same command can simultaneously write identical data to other logical units designated for redundancy, ensuring data reliability while simplifying the control mechanism compared to separate write operations.
3Loss of time
If simultaneous programming and erasing operations are performed across multiple units, then operational time is reduced, but control precision may be compromised
Solution Approach 1:
The patent segments the control process into distinct phases: address decoding, command distribution, and execution monitoring. Each logical unit receives the appropriate portion of the control signal independently, allowing simultaneous operations while maintaining precise control over each unit's specific programming or erasing operation through dedicated control pathways within the unified command structure.
Data Source
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AI summary
The present disclosure includes methods and devices for logical unit operation. One device embodiment includes a number of logical units, wherein each of the number of logical units has a unique address. The device includes control circuitry coupled to the number of logical units and configured optionally to control more than one of the number of logical units with one of a number of commands and one address.