Long-Channel Back-Side Power Rail With Dielectric Capping
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Solution Overview
Problem
Current semiconductor transistor devices face challenges with complex metal layer routing in the back-end-of-line (BEOL) process as the technology scales down beyond 3 nm, leading to increased mask requirements and voltage drop issues due to thinner metal wires.
Innovation Solution
The solution involves relocating the power rail from the front side to the back side of the semiconductor transistor device, allowing for relaxed metal layer routing, fewer masks, improved IR drop, and enlarged power rail and active region areas. This is achieved by incorporating a back-side power rail and recessed source/drain regions, along with a back-side dielectric cap to reduce cell capacitance and eliminate current leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If power rail is relocated to back side with recessed source/drain regions, then metal layer routing complexity is reduced and IR drop is improved, but manufacturing process complexity increases
Solution Approach 1:
The power rail is relocated from the front side to the back side of the semiconductor transistor device, utilizing the third dimension (depth/back side) to resolve routing complexity. This spatial reconfiguration allows power delivery without requiring additional metal layers on the front side, thereby reducing routing complexity while managing manufacturing challenges through controlled access openings.
2Loss of energy
If power rail is relocated to back side, then cell capacitance is reduced, but substrate manipulation complexity increases
Solution Approach 1:
The substrate is segmented into regions with different configurations: areas with access openings exposing the back side for power rail connection, and areas with protective layers for isolation. This segmentation allows selective capacitance reduction in active regions while managing substrate complexity through structured zonation.
Solution Approach 2:
Dielectric layers and protective films serve as intermediaries between the front side circuitry and the back side power rail. These intermediary layers enable electrical isolation and mechanical protection, reducing parasitic capacitance while simplifying substrate manipulation by providing controlled interfaces.
3Reliability
If access openings are formed to expose back side, then power rail connection is enabled, but current leakage risk increases
Solution Approach 1:
Dielectric liners and protective layers are deposited on the sidewalls and surfaces of the access openings before power rail formation. These preliminary protective structures prevent current leakage paths from forming, addressing the harmful effect before the power connection is established.
Solution Approach 2:
Thin dielectric films and liner layers line the access openings and power rail interfaces, providing flexible electrical isolation. These thin film barriers enable reliable power connection while preventing current leakage through the substrate or between adjacent structures.
Data Source
AI summary
A method of forming a semiconductor transistor device. The method comprises forming a channel structure over a substrate and forming a first source/drain structure and a second source/drain structure on opposite sides of the fin structure. The method further comprises forming a gate structure surrounding the fin structure. The method further comprises flipping and partially removing the substrate to form a back-side capping trench while leaving a lower portion of the substrate along upper sidewalls of the first source/drain structure and the second source/drain structure as a protective spacer. The method further comprises forming a back-side dielectric cap in the back-side capping trench.