Co-integrating Long Channel Transistors With Vertical FETs

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Solution Overview

Problem

The fabrication of long channel transistors in vertical channel transistor devices is challenging due to the need for taller fins, which are difficult to produce effectively in semiconductor wafer fabrication processes.

Innovation Solution

A method is developed to co-integrate short-channel vertical transistors and long-channel transistors by recessing a wide fin region, allowing for the formation of a long channel transistor using a similar process to that for a vertical channel transistor, involving the deposition of a recess mask, gate electrode, and source and drain regions, enabling the creation of a recessed channel gate structure.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Length of moving object

If taller fins are used to form long channel transistors, then the channel length is increased, but the fabrication difficulty increases significantly

Engineering Contradiction:
Improvechannel lengthVSAvoidfabrication difficulty
Core Design Contradiction:
Length of moving objectVSEase of manufacture

Solution Approach 1:

The patent transitions from forming long channels in the vertical dimension (taller fins) to forming them in the horizontal dimension (wider fins with recessed regions). By changing the geometric orientation from vertical to horizontal fin structures, the patent achieves long channel lengths without the fabrication challenges associated with tall vertical fins.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent divides the fin structure into multiple segments: a wider fin region that is selectively recessed to form the long channel, and a narrower fin region for the vertical channel transistor. This segmentation allows different fin geometries to coexist on the same substrate, enabling both long and short channel devices to be fabricated using the same process.

Inventive Principle:
Principle #1Segmentation

2Adaptability or versatility

If the same fabrication process is used for both short and long channel transistors, then process compatibility is improved, but the fin geometry control becomes more complex

Engineering Contradiction:
Improveprocess compatibilityVSAvoidfin geometry control
Core Design Contradiction:
Adaptability or versatilityVSManufacturing precision

Solution Approach 1:

The patent applies different fin geometries to different regions of the substrate. The first fin structure has a wider width designed for long channel transistors, while the second fin structure has a narrower width designed for vertical channel transistors. This local differentiation of fin qualities allows both device types to be fabricated using the same overall process sequence.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent performs preliminary patterning to create regions with different fin widths before the recess formation step. By pre-defining which regions will become wide fins and which will remain narrow, the patent simplifies subsequent processing steps and ensures that the recess operation affects only the intended regions.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS10243073B2Vertical channel field-effect transistor (FET) process compatible long channel transistors
Publication Date: 2019.03.26 INTERNATIONAL BUSINESS MACHINE CORPORATION
  • US10243073B2 patent drawing
  • US10243073B2 patent drawing
  • US10243073B2 patent drawing

AI summary

Embodiments of the present invention provide methods and systems for co-integrating a short-channel vertical transistor and a long-channel transistor. One method may include: from a starting substrate, forming a wide fin, wherein the wide fin comprises a wide active region; depositing a recess mask over a top surface of the starting substrate; recessing a long channel based on the deposited recess mask; depositing a gate electrode and a gate material, to form a gate structure; and forming SD contacts in an SD region of the long-channel transistor.