Long Gate Fabrication With Balanced Etch Loading for HV Devices
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Solution Overview
Problem
The semiconductor industry faces challenges in fabricating high voltage devices alongside core devices due to differences in feature sizes and insulation requirements, leading to complications in shared fabrication processes and increased noise and error issues in analog-to-digital converters (ADCs) due to non-uniform threshold voltages and charge carrier trapping at gate dielectric interfaces.
Innovation Solution
A method is introduced to form semiconductor devices with distinct gate structure densities by using long gate devices in high voltage areas, where dummy gate stacks are formed with varying lengths and capped with a gate top hard mask, and openings are created in the photoresist layer to balance etch loading, allowing for even processing across different device areas, enabling the replacement of planar high voltage devices with multi-gate counterparts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If planar high voltage devices are replaced with multi-gate high voltage devices, then device performance and integration are improved, but fabrication complexity and process compatibility deteriorate due to different feature sizes and insulation requirements
Solution Approach 1:
The workpiece is divided into distinct first and second device areas with different dummy gate stack densities. The first area contains dummy gate stacks at a first density while the second area contains dummy gate stacks at a second density, allowing separate optimization for different device types (core vs. high voltage devices) within the same fabrication process
Solution Approach 2:
Different regions of the workpiece are given different local characteristics through varying dummy gate stack densities. The first device area has a first dummy gate stack density optimized for core devices, while the second device area has a second dummy gate stack density optimized for high voltage devices, enabling location-specific process optimization
2Manufacturing precision
If dummy gate stacks are formed with varying densities in different areas, then process uniformity is improved, but photoresist layer thickness uniformity deteriorates
Solution Approach 1:
Openings are proactively formed in the photoresist layer over the second device area before the etching process to pre-compensate for the excessive photoresist thickness caused by higher dummy gate stack density. This preliminary action prevents the etch loading non-uniformity that would otherwise occur
Solution Approach 2:
Excess photoresist material is selectively removed by forming openings in the photoresist layer over the second device area. This extraction of material compensates for the thicker photoresist deposition in high-density dummy gate stack regions, restoring effective thickness uniformity for the etching process
3Object-affected harmful factors
If high voltage devices are fabricated with long gate structures, then noise and error in ADCs are reduced, but fabrication process compatibility with core devices deteriorates
Solution Approach 1:
The workpiece is segmented into first and second device areas that can accommodate different device geometries. The first area supports core devices with standard gate lengths while the second area supports high voltage devices with long gate structures, allowing both device types to be fabricated in the same process without mutual interference
Solution Approach 2:
The fabrication process is designed to be universal and accommodate multiple device types simultaneously. By using area-specific dummy gate stack densities and selective opening formation, the same fabrication process can produce both core devices and high voltage devices with different gate length requirements on the same workpiece
Data Source
AI summary
Semiconductor devices and methods of forming the same are provided. An example method includes providing a workpiece including a first dummy gate stack and a second dummy gate stack in a first area of the workpiece, a third dummy gate stack and a fourth dummy gate stack in a second area of the workpiece, a hard mask layer over each of the first dummy gate stack, the second dummy gate stack, the third dummy gate stack, and the fourth dummy gate stack. The method further includes depositing a photoresist (PR) layer over the workpiece to form a first PR layer portion over the first area and a second PR layer portion over the second area; and selectively forming a first opening through the second PR layer portion over the third dummy gate stack and a second opening through the second PR layer portion over the fourth dummy gate stack.